DRAM cell structure with buried surrounding capacitor and process for manufacturing the same
    1.
    发明申请
    DRAM cell structure with buried surrounding capacitor and process for manufacturing the same 有权
    具有埋置周围电容器的DRAM单元结构及其制造方法

    公开(公告)号:US20040021162A1

    公开(公告)日:2004-02-05

    申请号:US10210031

    申请日:2002-08-02

    Inventor: Ting-Shing Wang

    Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

    Abstract translation: 一种存储器件,包括半导体衬底和存储器单元阵列,每个单元与相邻单元电隔离并且包括由衬底形成的岛,所述岛具有顶部部分和至少一个侧壁部分,并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器,以及形成在该岛的顶部的晶体管,该晶体管包括形成于顶部表面的栅极氧化层,栅极 形成在栅极氧化物层上,以及形成在顶部的第一和第二扩散区域,第一扩散区域与第二扩散区域间隔开。

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