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282 条记录 (耗时 0.027 秒)

    Mirror contact capacitor
    1.
    发明授权
    Mirror contact capacitor 有权

    公开(公告)号：US09881925B2

    公开(公告)日：2018-01-30

    申请号：US15192121

    申请日：2016-06-24

    申请人： International Business Machines Corporation

    发明人： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

    IPC分类号： H01L27/108 ,  H01L29/06

    CPC分类号： H01L27/10829 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/0649

    摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

    Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed
    4.
    发明授权
    Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed 有权
    控制外延生长在eDRAM深沟和eDRAM上形成

    公开(公告)号：US09589965B1

    公开(公告)日：2017-03-07

    申请号：US15004216

    申请日：2016-01-22

    申请人： GLOBALFOUNDRIES INC.

    发明人： Melissa A. Smith ,  Sunit S. Mahajan ,  Herbert L. Ho

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10879

    摘要： Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

    摘要翻译： 提供了形成用于eDRAM的多晶硅填充深沟槽的方法。 该方法可以包括在衬底中形成多个多晶硅填充的深沟槽。 将外延延迟掺杂剂引入到沟槽的上部。 然后在衬底上形成多个翅片，其中每个多晶硅填充的深沟槽包括在其上延伸的对应的鳍。 至少在多晶硅填充的深沟槽上外延生长硅层。 在多晶硅填充的深沟槽中的掺杂剂用于控制硅层的外延生长，减少或防止在先进技术节点处的相邻鳍片和/或深沟槽的短路。

    ASYMMETRIC STRESSOR DRAM
    5.
    发明申请
    ASYMMETRIC STRESSOR DRAM 审中-公开
    不对称压力DRAM

    公开(公告)号：US20150348972A1

    公开(公告)日：2015-12-03

    申请号：US14291094

    申请日：2014-05-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10861 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

    摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stressor enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations.

    摘要翻译： 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 不对称应力器在漏极电压低时在电荷存储期间使身体区域具有低的漏电流，并且在读取和写入操作期间使能耦合到漏极区域的体电位和用于存取晶体管的较低阈值电压。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09059029B2

    公开(公告)日：2015-06-16

    申请号：US13782704

    申请日：2013-03-01

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yasuyuki Arai

    IPC分类号： H01L27/108 ,  H01L27/115

    CPC分类号： H01L29/7869 ,  H01L21/8239 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/1156 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    摘要： To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

    摘要翻译： 提供高度集成的半导体存储器件。 提供即使在不提供电力的情况下也能够保存存储的数据的半导体存储器件。 提供具有大量写入周期的半导体存储器件。 通过形成包括三维布置的两个晶体管和一个电容器的存储单元来增加存储单元阵列的积分度。 使用具有比硅更宽的带隙的宽间隙半导体，通过形成用于控制存储单元中的电容器的电荷量的晶体管，防止积蓄在电容器中的电荷泄漏。 因此，可以提供即使在未提供电力的情况下也可以保存存储的数据的半导体存储器件。

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20130228839A1

    公开(公告)日：2013-09-05

    申请号：US13782704

    申请日：2013-03-01

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Yasuyuki Arai

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7869 ,  H01L21/8239 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/1156 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    摘要： To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

    SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20130137239A1

    公开(公告)日：2013-05-30

    申请号：US13746304

    申请日：2013-01-21

    申请人： FUJITSU SEMICONDUCTOR LIMITED

    发明人： Hiroyuki OGAWA ,  Akihisa Yamaguchi

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10882 ,  H01L27/10891 ,  H01L27/10894

    摘要： A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.

    摘要翻译： 半导体存储装置包括：包括晶体管和电容器的存储单元; 位线 字线 以及包括第一和第二读出放大器的读出放大器，其中存储单元包括：共享第一辅助字线的第一存储单元组; 以及共享第二辅助字线的第二存储单元组，其中所述字线包括耦合到所述第一辅助字线的第一字线和耦合到所述第二辅助字线的第二字线，所述第一字线耦合到 第一字线接触区域中的第一辅助字线，第二字线在第二字线接触区域中耦合到第二辅助字线，位线包括耦合到两侧的第一读出放大器的第一和第二位线 的第一个字线接触区域。