公开(公告)号：US20140244967A1

公开(公告)日：2014-08-28

申请号：US13777297

申请日：2013-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Abstract translation: 提供了用于执行向量对齐指令的技术。 第一处理器中的标量寄存器文件被配置为与向第二处理器共享一个或多个寄存器值，所述寄存器值是根据在矢量对准指令中指定的Rt地址从标量寄存器文件访问的一个或多个寄存器值，其中开始 从共享寄存器值之一确定位置。 第二处理器中的对准电路被配置为根据向量对准指令将矢量寄存器文件（VRF）的起始Vu寄存器内的起始位置与VRF的最后一个Vu寄存器的结束位置之间标识的数据进行对准。 存储电路被配置为从对准电路中选择对准的数据，并根据由向量对准指令指定的对准存储地址将对准的数据存储在向量寄存器文件中。

公开(公告)号：US09632781B2

公开(公告)日：2017-04-25

申请号：US13777297

申请日：2013-02-26

Applicant: Qualcomm Incorporated

Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.