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    IMPLEMENTING SYNAPTIC LEARNING USING REPLAY IN SPIKING NEURAL NETWORKS
    1.
    发明申请
    IMPLEMENTING SYNAPTIC LEARNING USING REPLAY IN SPIKING NEURAL NETWORKS 审中-公开
    使用复制神经网络实现重复学习

    公开(公告)号：US20150134582A1

    公开(公告)日：2015-05-14

    申请号：US14494681

    申请日：2014-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Alexander LEVIN ,  Venkat RANGAN ,  Erik Christopher MALONE

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/049

    Abstract: Aspects of the present disclosure relate to methods and apparatus for training an artificial nervous system. According to certain aspects, timing of spikes of an artificial neuron during a training iteration are recorded, the spikes of the artificial neuron are replayed according to the recorded timing, during a subsequent training iteration, and parameters associated with the artificial neuron are updated based, at least in part, on the subsequent training iteration.

    Abstract translation: 本公开的方面涉及用于训练人造神经系统的方法和装置。 根据某些方面，记录在训练迭代期间人造神经元的尖峰时间，在随后的训练迭代期间根据所记录的定时重播人造神经元的尖峰，并且基于人造神经元相关参数进行更新， 至少部分地在随后的训练迭代中。

    IMPLEMENTING A NEURAL-NETWORK PROCESSOR
    2.
    发明申请
    IMPLEMENTING A NEURAL-NETWORK PROCESSOR 审中-公开
    实施神经网络处理器

    公开(公告)号：US20150269480A1

    公开(公告)日：2015-09-24

    申请号：US14300019

    申请日：2014-06-09

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Alexander LEVIN ,  Erik Christopher MALONE ,  Edward Hanyu LIAO

    IPC: G06N3/08

    CPC classification number: G06N3/08 ,  G06N3/049 ,  G06N3/063

    Abstract: Certain aspects of the present disclosure support a method and apparatus for implementing kortex neural network processor within an artificial nervous system. According to certain aspects, a plurality of spike events can be generated by a plurality of neuron unit processors of the artificial nervous system, and the spike events can be sent from a subset of the neuron unit processors to another subset of the neuron unit processors via a plurality of synaptic connection processors of the artificial nervous system.

    Abstract translation: 本公开的某些方面支持用于在人造神经系统内实现kortex神经网络处理器的方法和装置。 根据某些方面，可以由人造神经系统的多个神经元单元处理器产生多个尖峰事件，并且尖峰事件可以从神经元单元处理器的子集发送到神经元单元处理器的另一子集，经由 人造神经系统的多个突触连接处理器。

    IMPLEMENTING DELAYS BETWEEN NEURONS IN AN ARTIFICIAL NERVOUS SYSTEM
    4.
    发明申请
    IMPLEMENTING DELAYS BETWEEN NEURONS IN AN ARTIFICIAL NERVOUS SYSTEM 审中-公开
    在人造神经系统中实施神经元之间的延迟

    公开(公告)号：US20150046381A1

    公开(公告)日：2015-02-12

    申请号：US14084342

    申请日：2013-11-19

    Applicant: QUALCOMM Incorporated

    Inventor： Erik Christopher MALONE ,  Venkat RANGAN ,  Jeffrey Alexander LEVIN

    IPC: G06N3/02

    CPC classification number: G06N3/02 ,  G06N3/049

    Abstract: Methods and apparatus are provided for implementing delays in an artificial nervous system. Synaptic and/or axonal delays between a post-synaptic artificial neuron and one or more pre-synaptic artificial neurons may be accounted for at the post-synaptic artificial neuron. One example method for managing delay between neurons in an artificial nervous system generally includes receiving, at a post-synaptic artificial neuron, input current values from one or more pre-synaptic artificial neurons; accounting for delays between the one or more pre-synaptic artificial neurons and the post-synaptic artificial neuron at the post-synaptic artificial neuron; and determining a state of the post-synaptic artificial neuron based at least in part on at least a portion of the input current values, according to the accounting.

    Abstract translation: 提供了用于在人造神经系统中实施延迟的方法和装置。 突触后人工神经元和一个或多个突触前人工神经元之间的突触和/或轴突延迟可以在突触后人造神经元中被考虑。 用于管理人造神经系统中的神经元之间的延迟的一个示例性方法通常包括在突触后人造神经元处接收来自一个或多个突触前人造神经元的输入电流值; 考虑到在突触后人造神经元之间的一个或多个突触前人造神经元和突触后人造神经元之间的延迟; 以及至少部分地基于所述输入当前值的至少一部分来确定所述突触后人造神经元的状态。

    EFFICIENT HARDWARE IMPLEMENTATION OF SPIKING NETWORKS
    5.
    发明申请
    EFFICIENT HARDWARE IMPLEMENTATION OF SPIKING NETWORKS 有权
    SPI网络的有效硬件实现

    公开(公告)号：US20140351190A1

    公开(公告)日：2014-11-27

    申请号：US14267005

    申请日：2014-05-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： Jeffrey Alexander LEVIN ,  Venkat RANGAN ,  Erik Christopher MALONE

    IPC: G06N3/063 ,  G06N3/08

    CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/08

    Abstract: Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.

    Abstract translation: 本公开的某些方面支持在人造神经系统中同时操作多个超级神经元处理单元，其中将多个人造神经元分配给每个超级神经元处理单元。 超神经元处理单元可以与用于存储和加载人造神经系统的突触权重和可塑性参数的存储器接口，其中存储器的组织允许连续的存储器访问。

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