公开(公告)号：US20140264331A1

公开(公告)日：2014-09-18

申请号：US13800976

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M. Nowak ,  Glen T. Kim ,  Mark C. Chan ,  Shiqun Gu

IPC: H01L21/66

CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。

公开(公告)号：US09024315B2

公开(公告)日：2015-05-05

申请号：US13800976

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M Nowak ,  Glen T Kim ,  Mark C Chan ,  Shiqun Gu

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。