公开(公告)号：US12131997B2

公开(公告)日：2024-10-29

申请号：US17844337

申请日：2022-06-20

申请人： SK hynix Inc.

发明人： Won Duck Jung

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/5286 ,  H01L23/528 ,  H01L23/552 ,  H01L24/05 ,  H01L24/46 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US12131796B2

公开(公告)日：2024-10-29

申请号：US18195860

申请日：2023-05-10

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US20240355691A1

公开(公告)日：2024-10-24

申请号：US18761238

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC分类号： H01L23/31 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/3114 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/566 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  B29C45/14655 ,  B29K2063/00 ,  B29K2995/0007 ,  B29L2031/3406 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/3511

摘要： A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US12125825B2

公开(公告)日：2024-10-22

申请号：US16678619

申请日：2019-11-08

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Michael Carroll

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2924/181

摘要： The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

公开(公告)号：US12119238B2

公开(公告)日：2024-10-15

申请号：US16588588

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L21/563 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13172 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13172 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/11

摘要： A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

公开(公告)号：US20240339390A1

公开(公告)日：2024-10-10

申请号：US18666369

申请日：2024-05-16

申请人： Lodestar Licensing Group LLC

发明人： Owen R. Fay ,  Jack E. Murray

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181

摘要： Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US12113025B2

公开(公告)日：2024-10-08

申请号：US17881981

申请日：2022-08-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Hsien-Wen Liu ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/065

CPC分类号： H01L23/5385 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

公开(公告)号：US20240332252A1

公开(公告)日：2024-10-03

申请号：US18417411

申请日：2024-01-19

申请人： Meta Platforms Technologies, LLC

发明人： Jaspreet Singh Gandhi ,  Jaesik Lee ,  Rajendra D Pendse

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/4813 ,  H01L2224/48157 ,  H01L2224/73257 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/15311

摘要： A multi-chiplet assembly may include a first logic chiplet. A multi-chiplet assembly may include a memory chiplet electrically coupled to the first logic chiplet. A multi-chiplet assembly may include a second logic chiplet. A multi-chiplet assembly may include a bridging chiplet electrically coupling the first logic chiplet to the second logic chiplet. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US20240332032A1

公开(公告)日：2024-10-03

申请号：US18623233

申请日：2024-04-01

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Dong Jin Kim ,  Jin Han Kim ,  Won Chul Do ,  Jae Hun Bae ,  Won Myoung Ki ,  Dong Hoon Han ,  Do Hyung Kim ,  Ji Hun Lee ,  Jun Hwan Park ,  Seung Nam Son ,  Hyun Cho ,  Curtis Zwenger

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/92 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68304 ,  H01L2221/68318 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/81913 ,  H01L2224/81914 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161

摘要： A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

公开(公告)号：US20240321704A1

公开(公告)日：2024-09-26

申请号：US18680282

申请日：2024-05-31

申请人： TONGFU MICROELECTRONICS CO., LTD.

发明人： Maohua DU

IPC分类号： H01L23/498 ,  H01L21/603 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L21/603 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/182

摘要： A fan-out packaging method and packaging structure are provided. The method includes: fixing a first chip in a groove of a dummy chip where the first chip and the dummy chip are provided with a plurality of conductive through holes; bonding the second chip with the dummy chip and the first chip respectively; forming a plastic encapsulation layer to wrap the first chip, the dummy chip and the second chip; and forming a redistribution wiring layer on surfaces of the dummy chip and the first chip away from the second chip. The redistribution layer is electrically connected to the first chip through the plurality of conductive through holes.