公开(公告)号：US10332911B2

公开(公告)日：2019-06-25

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L21/84 ,  H01L23/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US10158030B2

公开(公告)日：2018-12-18

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Gengming Tao ,  Richard Hammond ,  Ranadeep Dutta ,  Matthew Michael Nowak ,  Francesco Carobolante

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US09633977B1

公开(公告)日：2017-04-25

申请号：US15040902

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Shiqun Gu ,  Urmi Ray ,  Ratibor Radojcic

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/10 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/92144 ,  H01L2924/19105 ,  H05K1/14 ,  H05K1/148 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

公开(公告)号：US20170098663A1

公开(公告)日：2017-04-06

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/768 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US09595496B2

公开(公告)日：2017-03-14

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/02 ,  H01L21/44 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：US20170063079A1

公开(公告)日：2017-03-02

申请号：US14838034

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Eugene Robert Worley ,  Ratibor Radojcic ,  Urmi Ray

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00012

Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract translation: 集成电路（IC）封装包括管芯，耦合到管芯的封装衬底以及耦合到封装衬底的第一静电放电（ESD）保护元件，其中第一静电放电（ESD）保护元件被配置为提供封装 级静电放电（ESD）保护。 在一些实施方案中，第一静电放电（ESD）保护组件嵌入在封装衬底中。 在一些实施方案中，管芯包括配置成提供管芯级静电放电（ESD）保护的内部静电放电（ESD）保护部件。 在一些实施方案中，内部静电放电（ESD）保护部件和第一静电放电（ESD）保护部件被配置为为管芯提供累积静电放电（ESD）保护。

公开(公告)号：US09478528B2

公开(公告)日：2016-10-25

申请号：US13771638

申请日：2013-02-20

Applicant: Qualcomm Incorporated

Inventor： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew M. Nowak

IPC: H01L25/16 ,  H01L25/00 ,  H04B10/80 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H04B10/803 ,  H01L2924/00012

Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.

Abstract translation: 一些实施方案提供包括第一管芯和光学接收器的半导体器件。 第一模具包括具有足够薄的厚度以允许光信号穿过背侧层的背面层。 光接收器被配置为通过第一管芯的背侧层接收多个光信号。 在一些实现中，每个光信号源自耦合到第二管芯的对应的光发射器。 在一些实施方式中，背面层是模具基板。 在一些实现中，光信号穿过背侧层的衬底部分。 第一裸片还包括有源层。 光接收器是有源层的一部分。 在一些实施方案中，半导体器件包括包括光发射器的第二裸片。 第二模具耦合到第一模具的背面。

公开(公告)号：US09418877B2

公开(公告)日：2016-08-16

申请号：US14324136

申请日：2014-07-04

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L23/14 ,  H01L25/10 ,  H01L23/15

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基底部分，第一管芯（例如，第一晶片级管芯）和第二管芯（例如，第二晶片级管芯）。 基部包括第一无机电介质层，位于第一无机电介质层中的第一组互连，不同于第一无机介电层的第二电介质层和第二介电层中的一组再分布金属层。 第一管芯耦合到基部的第一表面。 第二管芯耦合到基部的第一表面，第二管芯通过第一组互连件电耦合到第一管芯。

公开(公告)号：US09379201B2

公开(公告)日：2016-06-28

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L21/4763 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L21/768 ,  H01L29/872 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/304 ,  H01L23/48 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US09355904B2

公开(公告)日：2016-05-31

申请号：US14311405

申请日：2014-06-23

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Shiqun Gu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.

Abstract translation: 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 用于TSV应变消除的方法包括在衬底中限定通孔的通孔。 该方法还包括在空腔中沉积隔离层。 该方法还包括用导电材料填充空腔。 该方法还包括去除隔离层的一部分以形成凹陷部分。