公开(公告)号：US11662765B1

公开(公告)日：2023-05-30

申请号：US17574722

申请日：2022-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Christophe Avoinne ,  Xavier Loic Leloup ,  Michael David Jager

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.