公开(公告)号：US11493949B2

公开(公告)日：2022-11-08

申请号：US16832855

申请日：2020-03-27

Applicant: Qualcomm Incorporated

Inventor： Farrukh Aquil ,  Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Yong Xu

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/16

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.

公开(公告)号：US20170090546A1

公开(公告)日：2017-03-30

申请号：US14863890

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Michael Brunolli ,  Stephen Thilenius ,  Patrick Isakanian ,  Vaishnav Srinivas

IPC: G06F1/32 ,  G11C11/4074 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/4086 ,  G06F13/4243 ,  G11C7/1072 ,  G11C11/4074 ,  H04L25/0278 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

公开(公告)号：US20140266357A1

公开(公告)日：2014-09-18

申请号：US13831201

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vaishnav Srinivas ,  Jan Diffenderfer ,  Philip Michael Clovis ,  David Ian West

IPC: H03K5/159

CPC classification number: H03K5/159

Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。

公开(公告)号：US11120863B2

公开(公告)日：2021-09-14

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Vaishnav Srinivas ,  Mahalingam Nagarajan ,  Yong Xu

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/409 ,  G06F13/42

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US09633698B2

公开(公告)日：2017-04-25

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Vaishnav Srinivas ,  David Ian West ,  Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Jason Thurston

IPC: G06F11/00 ,  G11C5/14 ,  G06F11/07 ,  G06F11/10 ,  G01R31/317

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

公开(公告)号：US09438208B2

公开(公告)日：2016-09-06

申请号：US14299779

申请日：2014-06-09

Applicant: QUALCOMM Incorporated

Inventor： Shraddha Sridhar ,  Vaishnav Srinivas

IPC: H03K3/017 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle.

Abstract translation: 占空比校正电路包括上升沿可变延迟电路和下降沿可变延迟电路。 每个延迟电路的可变延迟取决于未被校正的时钟信号的未校正的占空比，其由占空比校正电路校正为具有期望占空比的校正时钟信号。

公开(公告)号：US20150221716A1

公开(公告)日：2015-08-06

申请号：US14688807

申请日：2015-04-16

Applicant: QUALCOMM, Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第 第一和第二电极。 电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。 第一电极耦合到第一电源轨，第三电极耦合到第二电源轨，并且第二电源轨具有比第一电源轨更高的电源电压。

公开(公告)号：US09041148B2

公开(公告)日：2015-05-26

申请号：US13917549

申请日：2013-06-13

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01G4/33 ,  H01G4/38 ,  H01G4/002

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括低压电容器和高压电容器。 低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极 电介质层在第二和第三电极之间。 高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚 层或第二电介质层。

公开(公告)号：US20140061642A1

公开(公告)日：2014-03-06

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract translation: 这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。 该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。 外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。 在所公开的方法的各个方面，外部互连由模具的包装保护。

公开(公告)号：US20180129267A1

公开(公告)日：2018-05-10

申请号：US15863155

申请日：2018-01-05

Applicant: QUALCOMM Incorporated

Inventor： Michael BRUNOLLI ,  Stephen THILENIUS ,  Patrick ISAKANIAN ,  Vaishnav Srinivas

IPC: G06F1/32 ,  H04L25/02 ,  G11C11/4074 ,  G11C7/10 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/4086 ,  G06F13/4243 ,  G11C7/1072 ,  G11C11/4074 ,  H04L25/0264 ,  H04L25/0278 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.