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    Coherent interconnect power reduction using hardware controlled split snoop directories
    1.
    发明授权
    Coherent interconnect power reduction using hardware controlled split snoop directories 有权

    公开(公告)号：US10606339B2

    公开(公告)日：2020-03-31

    申请号：US15259697

    申请日：2016-09-08

    Applicant: QUALCOMM Incorporated

    Inventor： Christophe Avoinne ,  Luc Montperrus ,  Philippe Boucard ,  Rakesh Kumar Gupta

    IPC: G06F1/3296 ,  G06F12/0831 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/54

    Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

    INTERCONNECTIONS FOR MODULAR DIE DESIGNS
    5.
    发明公开
    INTERCONNECTIONS FOR MODULAR DIE DESIGNS 审中-公开

    公开(公告)号：US20230325576A1

    公开(公告)日：2023-10-12

    申请号：US17655823

    申请日：2022-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Siddharth Kamdar ,  Christophe Avoinne ,  Sanjay Jaisingh Arya ,  Manav Shah

    IPC: G06F30/394 ,  G11C5/06 ,  G11C8/12

    CPC classification number: G06F30/394 ,  G11C5/06 ,  G11C8/12

    Abstract: Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

    Interconnections for modular die designs
    6.
    发明授权
    Interconnections for modular die designs 有权

    公开(公告)号：US11972189B2

    公开(公告)日：2024-04-30

    申请号：US17655823

    申请日：2022-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Siddharth Kamdar ,  Christophe Avoinne ,  Sanjay Jaisingh Arya ,  Manav Shah

    IPC: G11C5/06 ,  G06F30/394 ,  G11C8/12

    CPC classification number: G06F30/394 ,  G11C5/06 ,  G11C8/12

    Abstract: Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

    Coherent Interconnect Power Reduction Using Hardware Controlled Split Snoop Directories
    8.
    发明申请
    Coherent Interconnect Power Reduction Using Hardware Controlled Split Snoop Directories 审中-公开

    公开(公告)号：US20180067542A1

    公开(公告)日：2018-03-08

    申请号：US15259697

    申请日：2016-09-08

    Applicant: QUALCOMM Incorporated

    Inventor： Christophe Avoinne ,  Luc Montperrus ,  Philippe Boucard ,  Rakesh Kumar Gupta

    IPC: G06F1/32 ,  G06F9/54

    CPC classification number: G06F1/3296 ,  G06F1/32 ,  G06F9/54 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

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