公开(公告)号：US20170010325A1

公开(公告)日：2017-01-12

申请号：US14794635

申请日：2015-07-08

Applicant: QUALCOMM Incorporated

Inventor： Arul Subbarayan ,  Sachin Badole ,  Archana Matta ,  Madhura Hegde ,  Sergio Mier ,  Shankarnarayan Bhat ,  Michael Laisne ,  Glenn Mark Plowman ,  Prakash Krishnan

IPC: G01R31/317

CPC classification number: G01R31/31707 ,  G01R31/31718 ,  G01R31/31835 ,  G01R31/318371

Abstract: A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.

Abstract translation: 提供了一种用于自适应测试时间缩短的方法和装置。 该方法开始于在晶片或电子芯片上运行预定数量的结构测试。 一旦运行了预定数量的结构测试，就会收集通过/失败数据。 然后，该通过/失败数据用于确定一致地通过预定数量的结构测试中的哪一个。 然后将一致的通过的测试分组到测试向量中的切片中。 一旦分组完成，在测试未来大量晶圆或电子芯片的时候，会一直跳过测试。 如果确定需要进行测试的调整，则可以调制采样率。 此外，可以在电子芯片上执行对晶片执行的测试的补充，以确保完整的测试覆盖。