公开(公告)号：US12105139B2

公开(公告)日：2024-10-01

申请号：US17565284

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/287 ,  G01R31/2879 ,  G01R31/31718 ,  G01R31/318314

Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

公开(公告)号：US11852684B2

公开(公告)日：2023-12-26

申请号：US18194264

申请日：2023-03-31

Applicant: Optimal Plus Ltd.

Inventor： Leonid Gurov ,  Gal Peled ,  Dan Sebban ,  Shaul Teplinsky

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/318511 ,  G01R31/31718 ,  H01L22/12

Abstract: A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

公开(公告)号：US11733293B2

公开(公告)日：2023-08-22

申请号：US17210324

申请日：2021-03-23

Applicant: Changxin Memory Technologies, Inc.

Inventor： Tianchen Lu ,  Yuan Chieh Lee

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/2882 ,  G01R31/2856 ,  G01R31/31713 ,  G01R31/31718 ,  G01R31/31726

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

公开(公告)号：US20230258716A1

公开(公告)日：2023-08-17

申请号：US18129315

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Gerald Pasdast ,  Zuogo Wu ,  Narasimha Lanka ,  Lakshmipriya Seshan

IPC: G01R31/3183 ,  G01R31/317

CPC classification number: G01R31/318314 ,  G01R31/31712 ,  G01R31/31718

Abstract: Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.

公开(公告)号：US11719749B1

公开(公告)日：2023-08-08

申请号：US17076850

申请日：2020-10-22

Applicant: Cadence Design Systems, Inc.

Inventor： Tirumala Surya Prasad Annepu ,  Shai Fuss ,  Zeev Kirshenbaum

IPC: G01R31/317 ,  G06F30/20 ,  G06F9/4401

CPC classification number: G01R31/31718 ,  G01R31/31704 ,  G06F9/4406 ,  G06F30/20

Abstract: A computer implemented method may include executing a first simulation test for testing a device under test (DUT) and a corresponding test environment; saving a snapshot image of the DUT and of the corresponding test environment upon completion of initialization actions included in the first simulation test to configure the DUT; compiling a DUT part of a second simulation test into the saved snapshot image of the DUT to obtain a restore image for the DUT; loading the restore image of the DUT and restoring the snapshot image of the test environment; loading a test environment part of the second simulation test; and executing the second simulation test on the DUT and corresponding test environment.

公开(公告)号：US20180364302A1

公开(公告)日：2018-12-20

申请号：US15623366

申请日：2017-06-14

Applicant: Nuvoton Technology Corporation

Inventor： Long Chieu

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/2894 ,  G01R31/287 ,  G01R31/31707 ,  G01R31/31718

Abstract: A method for testing a plurality of electronic devices includes performing tests of up to m devices at a time to measure device parameters on a device tester configured to test up to m devices at a time, where m is an integer. After each test, the method includes performing statistical analysis of the measured device parameters for all tested devices to determine statistical data, including updated mean and standard deviation for each parameter, and storing only the statistical data, and not the measured device parameters. The method further includes determining new pass/fail limits for each device parameter based on the updated mean and standard deviation, and determining pass or fail of each device based on the new pass/fail limits for each device parameter.

公开(公告)号：US20180074123A1

公开(公告)日：2018-03-15

申请号：US15266604

申请日：2016-09-15

Applicant: Honeywell International Inc.

Inventor： Vlad Pambucol ,  Konstantin Lobastov ,  Peter Richard Rogers

IPC: G01R31/317

CPC classification number: G01R31/31701 ,  G01R22/061 ,  G01R22/10 ,  G01R31/31707 ,  G01R31/31718

Abstract: A system and method are provided for testing the ability of a meter to issue a notification to a utility head-end. The method comprises: entering the meter into a system test mode, wherein in system test mode the meter records actual data, actual events, and actual errors in an actual table in a memory, and the meter receives commands to induce simulated events and errors; receiving a command to induce an event or error in the meter; recording, in a test table in the memory of the meter, information indicative of the occurrence of the induced event or error; and transmitting to the utility head-end, while the meter remains in the system test mode, the information stored in the test table.

公开(公告)号：US09759767B2

公开(公告)日：2017-09-12

申请号：US14695112

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Paul J. Grzymkowski ,  Susan K. Lichtensteiger ,  Robert J. McMahon ,  Troy J. Perry ,  David M. Picozzi ,  Thomas G. Sopchak

IPC: G01R31/00 ,  G01R31/28 ,  G01R21/133 ,  G06F17/50 ,  G01R31/317

CPC classification number: G01R31/2894 ,  G01R21/133 ,  G01R31/31718 ,  G06F17/5045 ,  G06F2217/78

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

公开(公告)号：US20170154132A1

公开(公告)日：2017-06-01

申请号：US14954391

申请日：2015-11-30

Applicant: SYNOPSYS, INC.

Inventor： EMIL GIZDARSKI

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G01R31/26 ,  G01R31/31704 ,  G01R31/31718 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318583 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5081 ,  G06F2217/14 ,  G06F2217/78

Abstract: Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.

公开(公告)号：US09653330B1

公开(公告)日：2017-05-16

申请号：US15015535

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  John R. Goss ,  Robert J. McMahon ,  Troy J. Perry ,  Thomas G. Sopchak

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/66 ,  G06F17/50 ,  G01R31/317

CPC classification number: G01R31/31718 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

Abstract: Disclosed are methods for performing threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (SVB) to improve SVB accuracy and, thereby product yield and reliability. In the methods, a process distribution for an integrated circuit chip design is divided into process windows, each associated with a corresponding performance range and a corresponding minimum supply voltage. First performance measurements are acquired from first performance monitors associated with first transistors on chips manufactured according to the design. Based on the first performance measurements, the chips are assigned to groups corresponding to the process windows. Second performance measurements are also be acquired from second performance monitors associated with second transistors, which are on the chips and which have either a different VT-type or a different maximum fan-out than the first transistors. Based on the second performance measurements, a determination is made as to whether chip group reassignment is warranted.