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公开(公告)号：US20240248135A1
公开(公告)日：2024-07-25
申请号：US18304568
申请日：2023-04-21
IPC分类号： G01R31/3183
CPC分类号： G01R31/318385 , G01R31/318371
摘要： Techniques are provided for generating a physical test pattern that is framed within an Forward Error Correction (FEC)-encoded stream or sequence. Accordingly, in one embodiment, a method is provided that includes obtaining a physical layer test pattern for testing operation of a device; generating an FEC framed test pattern that embeds the physical layer test pattern into an FEC-encoded stream; and applying the FEC framed test pattern to the transceiver device to test physical layer operation of the device and to obtain FEC error statistics.
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公开(公告)号：US12007439B1
公开(公告)日：2024-06-11
申请号：US18149165
申请日：2023-01-03
发明人： Kuo-Min Liao , Tien-Yu Liao , Chien-Han Liao
IPC分类号： G01R31/3183 , G01R31/3193
CPC分类号： G01R31/318371 , G01R31/31932 , G01R31/31935
摘要： A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.
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公开(公告)号：US11846671B2
公开(公告)日：2023-12-19
申请号：US17730964
申请日：2022-04-27
发明人： Adrian Ispas
IPC分类号： G01R31/317 , G01R31/3183
CPC分类号： G01R31/31709 , G01R31/318371
摘要： A method for recovering data included in a digitally modulated signal is described. The digitally modulated signal includes a symbol sequence. The method includes providing a mathematical model of the digitally modulated signal, the mathematical model describing the digitally modulated signal in terms of the symbol sequence and describing the digitally modulated signal in terms of a step response and/or an impulse response, and wherein the mathematical model also takes disturbances into account; and processing the digitally modulated signal based on the mathematical model, thereby recovering the data included in the digitally modulated signal. The disturbances include a random disturbance component modelled as a Gaussian disturbance, and include an inter-symbol interference component modelled as Gaussian noise, and wherein a dependence of the at least one step response on the symbol sequence is neglected within the mathematical model. Further, a measurement instrument and a measurement system are described.
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公开(公告)号：US20180336017A1
公开(公告)日：2018-11-22
申请号：US15550281
申请日：2016-11-29
发明人： Li-Chien Ting , Shellly Ann Evans , Serena Chiang Caluya , Alexey Nikolaevich Peskov , Pavel Nikolarvich Migachev , Alexander Smimov , Oleg Kostyuchenko , David Y Yang , Roman Vladimirovich Rybalkin
IPC分类号： G06F8/34
CPC分类号： G06F8/34 , G01R31/318371 , G06F8/33 , G06F17/5045
摘要： The present disclosure relates to a computer-implemented method for use in an electronic design environment. Embodiments may include defining, using at least one processor, a grammar object system including one or more of objects, elements, values and relationships. Embodiments may include generating a technology grammar binary representation, based upon, at least in part, the grammar object system and receiving a technology ASCII representation. Embodiments may further include parsing at least one of the technology grammar binary representation and the technology ASCII representation to generate a technology binary representation and providing the technology binary representation to at least one of a graphical user interface or a database.
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公开(公告)号：US09857422B2
公开(公告)日：2018-01-02
申请号：US15063692
申请日：2016-03-08
发明人： Franco Motika , John D. Parker , Gerard M. Salem
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2834 , G01R31/31704 , G01R31/31724 , G01R31/318307 , G01R31/318371
摘要： Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format ‘streams’ of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.
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公开(公告)号：US20170193155A1
公开(公告)日：2017-07-06
申请号：US15400904
申请日：2017-01-06
发明人： Xijiang Lin , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318371 , G01R31/318307 , G01R31/318364 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5059
摘要： Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.
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公开(公告)号：US09689922B2
公开(公告)日：2017-06-27
申请号：US14137518
申请日：2013-12-20
发明人： Jinlei Liu , Zu-liang Zhang , Shu Li
IPC分类号： G01R31/3183 , G01R31/317 , H04L1/24
CPC分类号： G01R31/318307 , G01R31/31707 , G01R31/318314 , G01R31/318335 , G01R31/318371 , H04L1/243 , H04L1/244
摘要： A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design automation tool (EDA). The generated design test pattern and command/instruction is sent directly to an automated test equipment apparatus (ATE) over a UNIX or scripting language based, and/or a network based, communication pipeline. The ATE converts the sent design test pattern to an instance of the test pattern directly executable by the ATE. The ATE apparatus inputs test signals to each of the multiple electronic DUTs based on the executable test pattern. The ATE apparatus then receives, from each of the multiple electronic DUTs, a test result based on the input test signals. The ATE returns the received test result, and a report of an action responsive to the command/instruction to the EDA tool, which may then process the test results and report.
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公开(公告)号：US20170132103A1
公开(公告)日：2017-05-11
申请号：US15415331
申请日：2017-01-25
发明人： Shunichi Amano , Hisashi Miyashita , Hideki Tai
IPC分类号： G06F11/263 , G06F11/273
CPC分类号： G06F11/263 , G01R31/31835 , G01R31/318371 , G06F11/273
摘要： Provided is a generation device including: a test vector generation unit for selecting, for each of parameters to be included in a test vector, one value from among possible values for the parameter to generate test vectors whose combinations of values are different from each other; an extraction unit for extracting, as partial sequences each including one or more test vectors, portions of a series including the test vectors output by the test vector generation unit; and a test sequence generation unit for generating a test sequence based on the extracted partial sequences.
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公开(公告)号：US09391794B2
公开(公告)日：2016-07-12
申请号：US12363354
申请日：2009-01-30
IPC分类号： G06F19/00 , H04L12/26 , H04L1/24 , G01R31/317 , G01R31/3183 , G01R31/28 , G06F11/263 , G06F17/50
CPC分类号： H04L12/2697 , G01R31/28 , G01R31/2801 , G01R31/31708 , G01R31/3171 , G01R31/3183 , G01R31/318357 , G01R31/318371 , G06F11/263 , G06F17/5009 , H04L1/244 , H04L43/50
摘要： Various implementations of the invention provide methods and apparatuses for generating a test sequence for a driver and channel combination, wherein the driver is non-linear. In various implementations of the invention, a test sequence is generated that produces the worst or near worst error rate of the channel. With various implementations of the invention, voltage waves at the driver and impulse response waves of the channel are generated. In various implementations of the invention, the driver voltage waves and impulse response waves are simulated responses of the driver and channel to a digital signal input. With further implementations of the invention, receiver voltage waves are generated by combining the impulse response wave and the driver voltage waves. Subsequently, a test sequence is selected based upon the combined receiver voltage wave.
摘要翻译： 本发明的各种实现提供了用于产生用于驱动器和信道组合的测试序列的方法和装置，其中驱动器是非线性的。 在本发明的各种实施方式中，产生测试序列，其产生通道的最差或接近最差的错误率。 通过本发明的各种实施方式，产生了驱动器处的电压波和通道的脉冲响应波。 在本发明的各种实现中，驱动器电压波和脉冲响应波是驱动器和通道对数字信号输入的仿真响应。 通过本发明的进一步实现，通过组合脉冲响应波和驱动器电压波来产生接收器电压波。 随后，基于组合的接收器电压波选择测试序列。
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10.发明申请公开(公告)号：US20160033571A1
公开(公告)日：2016-02-04
申请号：US14502455
申请日：2014-09-30
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318371 , G01R31/3185 , G01R31/318533 , G01R31/318536 , G01R31/318544 , G01R31/318547 , G01R31/3187 , G06F11/0706 , G06F11/079 , G06F11/27
摘要： A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.
摘要翻译： 描述了使用逻辑内置自检（LBIST）系统和LBIST系统对集成电路进行故障根本原因识别的方法来执行根本原因识别。 该系统包括一个或多个信道扫描路径，与在测试周期期间执行的一个或多个信道扫描路径中的每一个相关联的一个或多个宏中的每一个，以及经由LBIST发起一个或多个测试周期的处理器 控制器，识别一个或多个测试周期中的故障测试周期，识别用于故障循环的一个或多个信道扫描路径中的故障通道扫描路径，识别与故障通道扫描路径相关联的一个或多个宏， 并迭代地检查与故障通道扫描路径相关联的一个或多个宏中的每一个以执行根本原因识别。
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