公开(公告)号：US20240113986A1

公开(公告)日：2024-04-04

申请号：US17937495

申请日：2022-10-03

Applicant: QUALCOMM Incorporated

Inventor： Narasimha Rao KORAMUTLA ,  Arun GOTHEKAR ,  Susheel Kumar Yadav YADAGIRI ,  Akshat GUPTA ,  Srinivas MARAKALA ,  Naveen Kumar NARALA ,  Radvajesh MUNIBYRAIAH

IPC: H04L47/62 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

CPC classification number: H04L47/624 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

Abstract: Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.