公开(公告)号：US20240205434A1

公开(公告)日：2024-06-20

申请号：US18066986

申请日：2022-12-15

Applicant: QUALCOMM Incorporated

Inventor： Tomoyuki NAITO ,  Yasutomo MATSUBA

IPC: H04N19/42 ,  H04N19/172 ,  H04N19/174 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N19/42 ,  H04N19/172 ,  H04N19/174 ,  H04N19/184 ,  H04N19/70

Abstract: Systems and techniques are described herein for processing video data. For instance, a process can include obtaining first encoded data for a first portion of an image, the image encoded in a plurality of independently decodable portions. The process can further include generating first intermediate data for the first portion of the image, storing the first intermediate data in a bitstream order, obtaining second encoded data for a second portion of the image, generating second intermediate data for the second portion of the image, storing the second intermediate data in the bitstream order, wherein the first intermediate data is stored separate from the second intermediate data, processing the first intermediate data and the second intermediate data in a raster scan order across the first portion of the image and the second portion of the image to generate a part of the image.

公开(公告)号：US20240298016A1

公开(公告)日：2024-09-05

申请号：US18177942

申请日：2023-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hua-I CHANG ,  Khalid TAHBOUB ,  Yasutomo MATSUBA ,  Kai WANG

IPC: H04N19/30 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/30 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: A device includes a decoder that includes a spatial prediction engine, a temporal prediction engine, a reconstruction engine, and a decoded picture buffer. The device also includes a controller configured to cause the decoder to, in a base resolution mode, reconstruct a base resolution version of a block of a frame using the reconstruction engine and at least one of the spatial prediction engine or the temporal prediction engine. The controller is also configured to cause the decoder to, in an enhanced resolution mode, generate an enhanced resolution version of the block using the reconstruction engine and the at least one of the spatial prediction engine or the temporal prediction engine.

公开(公告)号：US20220321899A1

公开(公告)日：2022-10-06

申请号：US17217745

申请日：2021-03-30

Applicant: QUALCOMM Incorporated

Inventor： Yasutomo MATSUBA ,  Kai WANG

IPC: H04N19/42 ,  H04N19/70 ,  H04N19/124 ,  H04N19/18 ,  H04N19/51 ,  H04N19/172 ,  H04N19/107

Abstract: A device includes a first bitstream engine and a second bitstream engine. The first bitstream engine is configured to decode a first portion of a first video frame of a plurality of video frames to generate first decoded portion data. The first bitstream engine is also configured to generate synchronization information based on completion of decoding the first portion. The second bitstream engine is configured to, based on the synchronization information, initiate decoding of a second portion of a particular video frame to generate second decoded portion data. The second bitstream engine uses the first decoded portion data during decoding of the second portion of the particular video frame. The particular video frame includes the first video frame or a second video frame of the plurality of video frames.

公开(公告)号：US20240236333A1

公开(公告)日：2024-07-11

申请号：US18150649

申请日：2023-01-05

Applicant: QUALCOMM Incorporated

Inventor： Tomoyuki NAITO ,  Yasutomo MATSUBA

IPC: H04N19/146 ,  H04N19/117 ,  H04N19/119 ,  H04N19/136 ,  H04N19/182

CPC classification number: H04N19/146 ,  H04N19/117 ,  H04N19/119 ,  H04N19/136 ,  H04N19/182

Abstract: Systems and techniques are described herein for processing video data. For instance, a process can include determining a number of rows of pixels for one or more portions of an image. The process can further include obtaining first encoded data for a first portion of the image, decoding the first encoded data to generate first pixel data for the number of rows of pixels of the first portion of the image, outputting the first pixel data for the first portion of the image to a memory, and outputting an indication that the first portion of the image is available.

公开(公告)号：US20240080474A1

公开(公告)日：2024-03-07

申请号：US17929548

申请日：2022-09-02

Applicant: QUALCOMM Incorporated

Inventor： Gopi Madhan DABBADI ,  Yasutomo MATSUBA ,  Sandeep Nellikatte SRIVATSA ,  Ashish MISHRA

IPC: H04N19/513 ,  H04N19/433 ,  H04N19/55 ,  H04N19/573

CPC classification number: H04N19/521 ,  H04N19/433 ,  H04N19/55 ,  H04N19/573

Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain one or more first sets of collocated motion vector data and one or more second sets of collocated motion vector data, associated with a respective first and second block of video data included in a current frame of video data. The apparatus may project the one or more first sets of collocated motion vector data into a first projected motion field associated with a first buffer and project the one or more second sets of collocated motion vector data into the first projected motion field associated with the first buffer. Based on projecting the one or more first sets and one or more second sets of collocated motion vector data, the apparatus may decode the first block of video data based on the first projected motion field associated with the first buffer.

公开(公告)号：US20190303174A1

公开(公告)日：2019-10-03

申请号：US16368301

申请日：2019-03-28

Applicant: QUALCOMM Incorporated

Inventor： Srikanth ALAPARTHI ,  Harikrishna REDDY ,  Yasutomo MATSUBA ,  Ashish MEDEWAR ,  Siddharth KHIMSARA

IPC: G06F9/445

Abstract: Systems and methods implemented in firmware and hardware domains may include writing by the firmware domain configuration information to a memory for a plurality of passes of hardware processing, programming by the hardware domain configuration registers with the configuration information retrieved from the memory, and processing by the hardware domain the plurality of passes in accordance with the configuration information programmed in the configuration registers. The configuration registers may be programmed after the configuration information are written to the memory.