公开(公告)号：US20190286590A1

公开(公告)日：2019-09-19

申请号：US15921092

申请日：2018-03-14

Applicant: QUANTA COMPUTER INC.

Inventor： Chi-Tsun CHOU ,  Ying-Che CHANG ,  Yen-Tse CHANG ,  Wen-Hua LO

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/28

Abstract: An example multi-node system that prevents multi-master issues on a common bus is disclosed. The system has a first node and a second node. A backplane is coupled to the first and second nodes via a system management bus. A complex programmable logic device is coupled to the system management bus. The complex programmable logic device includes hardware logic operable to arbitrate between bus commands from the first and second nodes.

公开(公告)号：US20190220340A1

公开(公告)日：2019-07-18

申请号：US15944139

申请日：2018-04-03

Applicant: QUANTA COMPUTER INC.

Inventor： Chi-Tsun CHOU ,  Ying-Che CHANG ,  Yen-Tse CHANG

IPC: G06F11/07 ,  G06F11/34 ,  G06F11/30 ,  G06F11/14

CPC classification number: G06F11/0757 ,  G06F11/1441 ,  G06F11/3058

Abstract: The present disclosure provides a system and method for resetting a hang-up baseboard management controller (BMC), or another component of a server system using a hardware watch-dog-timer (HW WDT) circuit and/or complex programmable logic device (CPLD). The HW WDT circuit can monitor heartbeat signals from the BMC, and determine the health condition of the BMC. In an event that the BMC's health condition fails to meet a predefined criterion, the HW WDT circuit generates a reset signal to reset the BMC. The CPLD can collect from the BMC, health information of components of the server system. The CPLD can also collect the BMC's health condition from the HW WDT circuit. Upon determining which specific component of the server system hangs up, the CPLD can generate a reset signal to reset the specific component.