利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.04 秒)

    LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES
    1.
    发明申请
    LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES 有权
    与金属顶电极组合的垂直互连的低成本方法

    公开(公告)号：US20110027986A1

    公开(公告)日：2011-02-03

    申请号：US12844347

    申请日：2010-07-27

    申请人： Raffaele VECCHIONE ,  Luigi Giuseppe OCCHIPINTI ,  Nunzia MALAGNINO ,  Rossana SCALDAFERRI ,  Maria Viviana VOLPE

    发明人： Raffaele VECCHIONE ,  Luigi Giuseppe OCCHIPINTI ,  Nunzia MALAGNINO ,  Rossana SCALDAFERRI ,  Maria Viviana VOLPE

    IPC分类号： H01L21/768

    CPC分类号： H01L51/0022

    摘要： A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.

    摘要翻译： 一种用于通过集成电路的上导电层和下导电层之间的介电层形成垂直互连的方法。 该方法包括通过介电层形成开口，并通过印刷技术将可固化的导电填料放入开口中。 可凝固的导电填料固化，从而在开口中形成凝固的导电填料。 在电介质层和凝固的导电填料上形成金属化层，从而通过集成电路的上导电层和下导电层之间的介电层形成垂直互连。