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    Low cost method of fabrication of vertical interconnections combined to metal top electrodes
    3.
    发明授权
    Low cost method of fabrication of vertical interconnections combined to metal top electrodes 有权
    制造与金属顶电极组合的垂直互连的低成本方法

    公开(公告)号：US08062976B2

    公开(公告)日：2011-11-22

    申请号：US12844347

    申请日：2010-07-27

    Applicant: Raffaele Vecchione ,  Luigi Giuseppe Occhipinti ,  Nunzia Malagnino ,  Rossana Scaldaferri ,  Maria Viviana Volpe

    Inventor： Raffaele Vecchione ,  Luigi Giuseppe Occhipinti ,  Nunzia Malagnino ,  Rossana Scaldaferri ,  Maria Viviana Volpe

    IPC: H01L21/4763

    CPC classification number: H01L51/0022

    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.

    Abstract translation: 一种用于通过集成电路的上导电层和下导电层之间的介电层形成垂直互连的方法。 该方法包括通过介电层形成开口，并通过印刷技术将可固化的导电填料放入开口中。 可凝固的导电填料固化，从而在开口中形成凝固的导电填料。 在电介质层和凝固的导电填料上形成金属化层，从而通过集成电路的上导电层和下导电层之间的介电层形成垂直互连。

    LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES
    6.
    发明申请
    LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES 有权
    与金属顶电极组合的垂直互连的低成本方法

    公开(公告)号：US20110027986A1

    公开(公告)日：2011-02-03

    申请号：US12844347

    申请日：2010-07-27

    Applicant: Raffaele VECCHIONE ,  Luigi Giuseppe OCCHIPINTI ,  Nunzia MALAGNINO ,  Rossana SCALDAFERRI ,  Maria Viviana VOLPE

    Inventor： Raffaele VECCHIONE ,  Luigi Giuseppe OCCHIPINTI ,  Nunzia MALAGNINO ,  Rossana SCALDAFERRI ,  Maria Viviana VOLPE

    IPC: H01L21/768

    CPC classification number: H01L51/0022

    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.

    Abstract translation: 一种用于通过集成电路的上导电层和下导电层之间的介电层形成垂直互连的方法。 该方法包括通过介电层形成开口，并通过印刷技术将可固化的导电填料放入开口中。 可凝固的导电填料固化，从而在开口中形成凝固的导电填料。 在电介质层和凝固的导电填料上形成金属化层，从而通过集成电路的上导电层和下导电层之间的介电层形成垂直互连。

    PROCESS FOR MANUFACTURING A NON-VOLATILE MEMORY STRUCTURE VIA SOFT LITHOGRAPHY
    7.
    发明申请
    PROCESS FOR MANUFACTURING A NON-VOLATILE MEMORY STRUCTURE VIA SOFT LITHOGRAPHY 有权
    通过软绘图制造非易失性存储器结构的过程

    公开(公告)号：US20070243679A1

    公开(公告)日：2007-10-18

    申请号：US11697990

    申请日：2007-04-09

    Applicant: Raffaele Vecchione ,  Roberta Cuozzo ,  Anna Morra ,  Teresa Napolitano

    Inventor： Raffaele Vecchione ,  Roberta Cuozzo ,  Anna Morra ,  Teresa Napolitano

    IPC: H01L21/8242

    CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  G11C2213/77 ,  H01L51/0022 ,  H01L2251/105

    Abstract: A process for manufacturing a non-volatile memory structure, in particular of a cross-point type provided with an array of memory cells, including forming bottom electrodes on a substrate; forming areas of active material on the bottom electrodes; and forming top electrodes on the areas of active material. The memory cells are defined at the intersection of the bottom electrode with the top electrode. At least one from among the steps of forming bottom electrodes, forming areas of active material, and forming top electrodes includes using soft-lithography techniques, chosen from amongst “microtransfer molding”, “micromolding in capillary”, and “microcontact printing”. According to a first type of structure, the step of forming areas of active material includes forming strips of active material in a way self-aligned with respect to the bottom electrodes or the top electrodes; according to a different type of structure, the step of forming areas of active material envisages forming monolayer or multilayer pads between the bottom electrodes and the top electrodes.

    Abstract translation: 一种用于制造非易失性存储器结构的方法，特别是具有存储单元阵列的交叉点型，包括在衬底上形成底部电极; 在底部电极上形成活性材料区域; 并在活性材料的区域上形成顶部电极。 存储单元被限定在底部电极与顶部电极的交叉处。 从形成底部电极，形成活性材料的区域和形成顶部电极的步骤中的至少一个包括使用从“微转移成型”，“毛细管中的微成型”和“微接触印刷”中选择的软光刻技术。 根据第一类型的结构，形成活性材料区域的步骤包括以相对于底部电极或顶部电极自对准的方式形成活性材料条带; 根据不同类型的结构，形成活性材料区域的步骤设想在底部电极和顶部电极之间形成单层或多层焊盘。

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