公开(公告)号：US12112063B1

公开(公告)日：2024-10-08

申请号：US17481851

申请日：2021-09-22

Applicant: Rambus Inc.

Inventor： Michael Thomas Imel ,  Larry Arbuthnot ,  Charles J. Wilson

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/1626 ,  G06F13/1631

Abstract: A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.

公开(公告)号：US12261625B2

公开(公告)日：2025-03-25

申请号：US17548176

申请日：2021-12-10

Applicant: Rambus Inc.

Inventor： Michael Thomas Imel

IPC: H03M13/11 ,  H03M13/19

Abstract: An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m

公开(公告)号：US20250077124A1

公开(公告)日：2025-03-06

申请号：US18882333

申请日：2024-09-11

Applicant: Rambus Inc.

Inventor： Michael Thomas Imel ,  Larry Arbuthnot ,  Charles J. Wilson

IPC: G06F3/06 ,  G06F13/16

Abstract: A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.

公开(公告)号：US20220190846A1

公开(公告)日：2022-06-16

申请号：US17548176

申请日：2021-12-10

Applicant: Rambus Inc.

Inventor： Michael Thomas Imel

IPC: H03M13/11 ,  H03M13/19

Abstract: An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m