公开(公告)号：US08938578B2

公开(公告)日：2015-01-20

申请号：US13936777

申请日：2013-07-08

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Renu Rangnekar

IPC: G06F12/00 ,  G11C11/4063 ,  G11C7/10

CPC classification number: G11C11/4063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal.

Abstract translation: 公开了一种集成电路存储器件。 存储器件包括具有用于接收时钟信号的定时输入的存储器芯。 接口耦合到内存核心。 该接口包括用于接收写入数据位的串行流的接收器和由选通信号计时的采样器，以产生串行化写入数据。 该接口还包括解串器和控制逻辑。 解串器包括用于接收串行写入数据的输入端和响应于由控制逻辑产生的控制信号产生并行数据的输出端。 在第一操作模式中，控制逻辑产生相对于时钟信号的控制信号。 在第二操作模式中，控制逻辑产生关于选通信号的控制信号。

公开(公告)号：US20140029331A1

公开(公告)日：2014-01-30

申请号：US13936777

申请日：2013-07-08

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Renu Rangnekar

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal.

Abstract translation: 公开了一种集成电路存储器件。 存储器件包括具有用于接收时钟信号的定时输入的存储器芯。 接口耦合到内存核心。 该接口包括用于接收写入数据位的串行流的接收器和由选通信号计时的采样器，以产生串行化写入数据。 该接口还包括解串器和控制逻辑。 解串器包括用于接收串行写入数据的输入端和响应于由控制逻辑产生的控制信号产生并行数据的输出端。 在第一操作模式中，控制逻辑产生相对于时钟信号的控制信号。 在第二操作模式中，控制逻辑产生关于选通信号的控制信号。