公开(公告)号：US12046321B2

公开(公告)日：2024-07-23

申请号：US17651597

申请日：2022-02-18

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Geyan Liu

IPC分类号： G11C7/10 ,  G11C5/06 ,  G11C11/4063 ,  G11C11/4072

CPC分类号： G11C7/1078 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4063 ,  G11C11/4072

摘要： A compilation method includes the following: receiving a signal to be compiled and a resistance matching signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and in the case where the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal according to the resistance matching signal to determine a first compiled value.

公开(公告)号：US11966814B2

公开(公告)日：2024-04-23

申请号：US18101522

申请日：2023-01-25

申请人： Google LLC

发明人： Craig Gidney ,  Austin Greig Fowler

IPC分类号： G11C11/40 ,  G06F7/48 ,  G06F7/505 ,  G06F7/72 ,  G06F17/10 ,  G06N10/00 ,  G11C11/4063 ,  H04B10/70

CPC分类号： G06N10/00 ,  G06F7/4824 ,  G06F7/505 ,  G06F7/5057 ,  G06F7/72 ,  G06F17/10 ,  G11C11/4063 ,  H04B10/70

摘要： Methods and apparatus for performing surface code computations using Auto-CCZ states. In one aspect, a method for implementing a delayed choice CZ operation on a first and second data qubit using a quantum computer includes: preparing a first and second routing qubit in a magic state; interacting the first data qubit with the first routing qubit and the second data qubit with the second routing qubit using a first and second CNOT operation, where the first and second data qubits act as controls for the CNOT operations; if a received first classical bit represents an off state: applying a first and second Hadamard gate to the first and second routing qubit; measuring the first and second routing qubit using Z basis measurements to obtain a second and third classical bit; and performing classically controlled fixup operations on the first and second data qubit using the second and third classical bits.

公开(公告)号：US11842760B2

公开(公告)日：2023-12-12

申请号：US17945956

申请日：2022-09-15

申请人： Rambus Inc.

发明人： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC分类号： G11C11/40 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/40 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

摘要： An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US20230281497A1

公开(公告)日：2023-09-07

申请号：US18111413

申请日：2023-02-17

申请人： Google LLC

发明人： Craig Gidney

IPC分类号： G06N10/00 ,  G11C11/4063 ,  G06F7/48 ,  G06F7/72 ,  G06F7/505 ,  G06F17/10 ,  H04B10/70

CPC分类号： G06N10/00 ,  G06F7/4824 ,  G06F7/505 ,  G06F7/5057 ,  G06F7/72 ,  G06F17/10 ,  G11C11/4063 ,  H04B10/70

摘要： Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.

公开(公告)号：US11688477B2

公开(公告)日：2023-06-27

申请号：US17502477

申请日：2021-10-15

申请人： Micron Technology, Inc.

发明人： Joseph T. Pawlowski

IPC分类号： G11C11/00 ,  G11C16/34 ,  G11C11/4063 ,  G06F12/02

CPC分类号： G11C16/349 ,  G06F12/0246 ,  G11C11/4063 ,  G06F2212/7201 ,  G06F2212/7211

摘要： Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

公开(公告)号：US20230162778A1

公开(公告)日：2023-05-25

申请号：US18158316

申请日：2023-01-23

申请人： Micron Technology, Inc.

发明人： Sujeet Ayyapureddi

IPC分类号： G11C11/406 ,  G11C11/4063

CPC分类号： G11C11/40615 ,  G11C11/4063 ,  G11C11/40622 ,  G11C11/40618

摘要： Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

公开(公告)号：US20190096451A1

公开(公告)日：2019-03-28

申请号：US16200443

申请日：2018-11-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  H03K19/0175 ,  H03K19/003 ,  G11C11/4063

CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/50012 ,  H03K19/003 ,  H03K19/017509

摘要： Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

公开(公告)号：US20180190341A1

公开(公告)日：2018-07-05

申请号：US15830314

申请日：2017-12-04

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-geun DO ,  Jong-ho LEE ,  Chan-yong LEE ,  Min-soo JANG

IPC分类号： G11C11/406 ,  G11C11/4063

CPC分类号： G11C11/40615 ,  G11C11/40618 ,  G11C11/4063 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.

公开(公告)号：US10014860B2

公开(公告)日：2018-07-03

申请号：US15629265

申请日：2017-06-21

申请人： Rambus Inc.

发明人： Ian Shaeffer

IPC分类号： H03K19/00 ,  G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  H03K19/0175 ,  G11C11/4063 ,  G11C11/413

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

摘要： Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20180144789A1

公开(公告)日：2018-05-24

申请号：US15584591

申请日：2017-05-02

申请人： SK hynix Inc.

发明人： Sun Hye SHIN

IPC分类号： G11C11/419 ,  G11C7/22 ,  G11C11/413 ,  G11C5/14 ,  G11C5/02 ,  G06F1/26 ,  G11C13/00

CPC分类号： G11C11/419 ,  G06F1/26 ,  G11C5/02 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4063 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/413 ,  G11C13/0069 ,  G11C2207/005 ,  G11C2207/2227 ,  G11C2213/53

摘要： A semiconductor device may be provided. The semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. The active signal may be divided into a read active signal generated based on a read command and a write active signal generated based on a write command.