公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US12087387B2

公开(公告)日：2024-09-10

申请号：US17750690

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Poornima Venkatasubramanian ,  Manish Chandra Joshi ,  Ved Prakash ,  Pushp Khatter

IPC: G11C7/10 ,  H03K3/037

CPC classification number: G11C7/1039 ,  G11C7/1066 ,  G11C7/1093 ,  H03K3/0372

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

公开(公告)号：US20240289047A1

公开(公告)日：2024-08-29

申请号：US18412731

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  G06F2213/16 ,  G11C7/1015 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US12068055B2

公开(公告)日：2024-08-20

申请号：US17899417

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Abhilash Ramamurthy Nag ,  Suresh Reddy Yarragunta ,  Shiva Pahwa

IPC: G11C7/10 ,  G06F11/30 ,  G06N20/00 ,  G11C29/00 ,  G11C29/52

CPC classification number: G11C7/1096 ,  G06F11/3058 ,  G06N20/00 ,  G11C7/1093 ,  G11C29/00 ,  G11C29/52 ,  G11C2207/2245 ,  G11C2207/229

Abstract: Exemplary methods, apparatuses, and systems include an environmental operations manager for controlling memory access of the memory device. The environmental operations manager receives a set of data bits for programming to a memory location. The environmental operations manager receives environmental condition data. The environmental operations manager delays programming of the set of data bits to the memory location and writing the set of data bits to a buffer location in response to determining that the environmental condition data satisfies a threshold.

公开(公告)号：US20240265955A1

公开(公告)日：2024-08-08

申请号：US18164570

申请日：2023-02-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shun-Ke Wu

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096

Abstract: An electronic device, a memory device of the electronic device, and a write leveling method of the memory device are provided. The memory device is coupled to a memory controller to receive a data strobe signal DQS and a clock signal CLK. In a write leveling mode, the memory device provides a write leveling function to the memory controller, where the write leveling function includes a plurality of iterative operations. In each of the iterative operations, the memory controller sends a notification to the memory device, and the memory device sets up a strobe window based on the notification. The memory device samples the clock signal CLK based on a phase of the data strobe signal DQS in the strobe window, so as to send a sampling result back to the memory controller. The memory device is prohibited from sampling the clock signal CLK outside the strobe window.

公开(公告)号：US20240257863A1

公开(公告)日：2024-08-01

申请号：US18584371

申请日：2024-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20240257849A1

公开(公告)日：2024-08-01

申请号：US18630352

申请日：2024-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soong-Man SHIN ,  Hyungjin KIM ,  YoungWook KIM

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18

Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.

公开(公告)号：US20240242747A1

公开(公告)日：2024-07-18

申请号：US18154860

申请日：2023-01-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chang-Ting Wu

IPC: G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/1093

Abstract: An off-chip driving device and a driving capability enhancement method thereof are provided. Detecting a rising edge and a falling edge of an input data signal. A first enhancement circuit is controlled to provide a first enhancement signal to an input/output pad according to the rising edge and the falling edge of the input data signal.

公开(公告)号：US20240242746A1

公开(公告)日：2024-07-18

申请号：US18416770

申请日：2024-01-18

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093

Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

公开(公告)号：US12040046B2

公开(公告)日：2024-07-16

申请号：US18447950

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Hoon Jang ,  Kyungryun Kim ,  Young Ju Kim ,  Seung-Jun Lee ,  Youngbin Lee ,  Yeonkyu Choi

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.