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公开(公告)号：US09906335B2
公开(公告)日：2018-02-27
申请号：US15361152
申请日：2016-11-25
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
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公开(公告)号：US20180248661A1
公开(公告)日：2018-08-30
申请号：US15872885
申请日：2018-01-16
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
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公开(公告)号：US20170187498A1
公开(公告)日：2017-06-29
申请号：US15361152
申请日：2016-11-25
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
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公开(公告)号：US20130202061A1
公开(公告)日：2013-08-08
申请号：US13729210
申请日：2012-12-28
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran
IPC: H04L25/06
CPC classification number: H04L25/06 , H04L25/063
Abstract: As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal. As a result, the receiver provides for reading received single-ended data in a manner enabling accurate data transfer at higher speeds.
Abstract translation: 由于单端信令在高速通信中实现，数据信号的精确和一致的读取变得越来越具有挑战性。 特别地，单端链路可能受到用于对接收的输入信号进行采样的定时裕度不足的限制。 单端接收器通过调整用于采样输入信号的参考电压来提供改进的定时裕度。 将校准模式作为输入信号提供给接收器，并且将参考电压朝向信号的中值调整。 结果，接收机提供以更高速度进行精确数据传输的方式读取接收到的单端数据。
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公开(公告)号：US10320534B2
公开(公告)日：2019-06-11
申请号：US15872885
申请日：2018-01-16
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
Abstract: An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.
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Patent Agency Ranking
公开(公告)号：US09537617B2
公开(公告)日：2017-01-03
申请号：US15019483
申请日：2016-02-09
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。
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公开(公告)号：US20160233991A1
公开(公告)日：2016-08-11
申请号：US15019483
申请日：2016-02-09
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
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公开(公告)号：US08923442B2
公开(公告)日：2014-12-30
申请号：US13729210
申请日：2012-12-28
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran
IPC: H04L25/06
CPC classification number: H04L25/06 , H04L25/063
Abstract: As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal.
Abstract translation: 由于单端信令在高速通信中实现，数据信号的精确和一致的读取变得越来越具有挑战性。 特别地，单端链路可能受到用于对接收的输入信号进行采样的定时裕度不足的限制。 单端接收器通过调整用于采样输入信号的参考电压来提供改进的定时裕度。 将校准模式作为输入信号提供给接收器，并且将参考电压朝向信号的中值调整。
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公开(公告)号：US09444442B2
公开(公告)日：2016-09-13
申请号：US14165370
申请日：2014-01-27
Applicant: RAMBUS INC.
CPC classification number: H03K5/1565
Abstract: A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.
Abstract translation: 相位插值器（PI）可以用作发送路径中的精确控制的延迟元件，例如在时钟转发的串行链路中。 公开了用于估计校正所接收时钟的占空比和/或相位误差所需的延迟的方法和电路。 这些校正或增量值可以被发送回发射机侧，优选地以PI相位代码直接表示，以便在发射机时钟电路中进行便利的调整。 公开了用于测量和减轻对PI积分非线性的影响的各种技术。
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公开(公告)号：US09294262B2
公开(公告)日：2016-03-22
申请号：US14722995
申请日：2015-05-27
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
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