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    Receiver clock test circuitry and related methods and apparatuses
    2.
    发明授权
    Receiver clock test circuitry and related methods and apparatuses 有权

    公开(公告)号：US09906335B2

    公开(公告)日：2018-02-27

    申请号：US15361152

    申请日：2016-11-25

    Applicant: Rambus Inc.

    Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

    IPC: H03H7/30 ,  H04L1/20 ,  H04L7/00 ,  H04L7/10

    CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

    Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

    System and method for parallel testing of multiple data packet signal transceivers
    5.
    发明授权
    System and method for parallel testing of multiple data packet signal transceivers 有权
    用于并行测试多个数据包信号收发器的系统和方法

    公开(公告)号：US08842549B2

    公开(公告)日：2014-09-23

    申请号：US13716369

    申请日：2012-12-17

    Applicant: Litepoint Corporation

    Inventor： Christian Volf Olgaard ,  Ruizu Wang ,  Erdem Serkan Erdogan ,  Mathew Philip

    IPC: H04W24/00 ,  H04L12/26

    CPC classification number: H04W24/00 ,  H04L1/1867 ,  H04L1/241 ,  H04L43/50 ,  H04W24/06

    Abstract: System and method for facilitating testing of multiple data packet signal transceivers involving data-packet-signal replication and one or more status signals indicating successful and unsuccessful receptions of confirmation signals. Based upon the one or more status signals, one or more control signals cause the replicated data packet signals to be distributed to the devices under test (DUTs) such that, following successful and unsuccessful receptions of confirmation signals, corresponding replicated data packet signals are caused to fail to conform in part or to conform, respectively, with a predetermined data packet signal standard.

    Abstract translation: 涉及涉及数据分组信号复制的多个数据分组信号收发机的测试的系统和方法以及表示确认信号的成功和不成功接收的一个或多个状态信号。 基于一个或多个状态信号，一个或多个控制信号使得复制的数据分组信号被分配到被测设备（DUT），使得在成功和不成功接收到确认信号之后，引起相应的复制数据分组信号 分别不符合预定的数据分组信号标准。

    CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA
    6.
    发明申请
    CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA 有权
    发送运行长度有限数据中的分类错误

    公开(公告)号：US20140223270A1

    公开(公告)日：2014-08-07

    申请号：US13761427

    申请日：2013-02-07

    Applicant: LSI CORPORATION

    Inventor： Coralyn S. Gauvin ,  Gabriel L. Romero

    IPC: G06F11/08

    CPC classification number: G01R31/3193 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/08 ,  G06F11/277 ,  H04L1/241

    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

    Abstract translation: 测试模式使用游程长度限制行编码来编码以产生编码的数据块。 编码的数据块通过信道发送。 在发送数据中的最大长度运行之后的所接收的数据块中的多个比特与预期的多个比特进行比较。 基于预期的多个比特和接收的数据块中的多个比特之间的不匹配来分类一种比特错误。

    UNIVERSAL TEST SYSTEM FOR TESTING ELECTRICAL AND OPTICAL HOSTS
    8.
    发明申请
    UNIVERSAL TEST SYSTEM FOR TESTING ELECTRICAL AND OPTICAL HOSTS 有权
    通用电气和光学测试系统

    公开(公告)号：US20130162279A1

    公开(公告)日：2013-06-27

    申请号：US13335661

    申请日：2011-12-22

    Applicant: D. Brice Achkir ,  Marco Mazzini ,  Stefano Riboldi ,  Cristiana Muzio

    Inventor： D. Brice Achkir ,  Marco Mazzini ,  Stefano Riboldi ,  Cristiana Muzio

    IPC: G01R31/00

    CPC classification number: G01R1/067 ,  G01R31/3185 ,  H04L1/241 ,  H04L1/243

    Abstract: According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode.

    Abstract translation: 根据示例实现，通用测试器包括在电测试操作模式期间连接到第一可插拔主机卡的主机接口插槽，以向被测试主机提供受压电信号。 在光学测试操作模式期间，主机接口插槽连接到第二可插拔主机卡，第二可插拔主机卡包括电光转换模块，用于将应力电信号转换为被提供给主机的应力光信号 测试。 压力发生器可以在直通模式或环回模式下操作。

    Duty cycle distortion (DCD) jitter modeling, calibration and generation methods
    9.
    发明授权
    Duty cycle distortion (DCD) jitter modeling, calibration and generation methods 有权
    占空比失真（DCD）抖动建模，校准和生成方法

    公开(公告)号：US08125259B2

    公开(公告)日：2012-02-28

    申请号：US11968942

    申请日：2008-01-03

    Applicant: Xingdong Dai ,  Weiwei Mao ,  Max J. Olsen ,  Geoffrey Zhang

    Inventor： Xingdong Dai ,  Weiwei Mao ,  Max J. Olsen ,  Geoffrey Zhang

    IPC: H03K3/017

    CPC classification number: H04L1/241 ,  H03M9/00 ,  H04L1/205

    Abstract: A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.

    Abstract translation: 一种用于建模和校准串行器和解串器（SerDes）器件的占空比失真（DCD）的方法和系统，包括首先产生时钟DCD信号。 一旦产生时钟DCD信号，它就是根据从时钟DCD信号的滤波处理获得的结果进行校准。 一旦时钟DCD信号被校准，基于从数据DCD信号的滤波处理获得的结果来产生和校准数据DCD信号。

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