公开(公告)号：US09507731B1

公开(公告)日：2016-11-29

申请号：US14512254

申请日：2014-10-10

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Joseph James Tringali ,  Vidyabhushan Mohan

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/109 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/657

Abstract: A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined to contain, in a location indicated by the cache line address, a cache line corresponding to the memory address, the cache line is retrieved from the location indicated by the cache line address.

Abstract translation: 与从缓存数据阵列检索数据的请求相关联地接收存储器地址和虚拟高速缓存标识符。 基于虚拟高速缓存标识符来选择上下文信息，上下文信息指示高速缓存数据阵列内的多个区域的第一区域。 生成包括根据第一区域的大小的存储器地址的第一位数的高速缓存行地址，并且如果高速缓存数据阵列被确定为包含在由高速缓存线地址指示的位置中的高速缓存 对应于存储器地址的行，从由高速缓存行地址指示的位置检索高速缓存行。