公开(公告)号：US20070250669A1

公开(公告)日：2007-10-25

申请号：US11380020

申请日：2006-04-25

申请人： Ravi Arimilli ,  Thomas Capasso ,  Robert Cargnoni ,  Guy Guthrie ,  Hugh Shen ,  William Starke

发明人： Ravi Arimilli ,  Thomas Capasso ,  Robert Cargnoni ,  Guy Guthrie ,  Hugh Shen ,  William Starke

IPC分类号： G06F13/00

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/544

摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

公开(公告)号：US20070250668A1

公开(公告)日：2007-10-25

申请号：US11380018

申请日：2006-04-25

申请人： Ravi Arimilli ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  William Starke

发明人： Ravi Arimilli ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  William Starke

IPC分类号： G06F13/00

CPC分类号： G06F13/1631 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0888

摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.

摘要翻译： 数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。 数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。 访问内存子系统的存储操作与第一个设置或第二个设置相关联。 数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成 在同步操作之后的存储操作之前。

公开(公告)号：US20050251660A1

公开(公告)日：2005-11-10

申请号：US10840560

申请日：2004-05-06

申请人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3861

摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

摘要翻译： 一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。 处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。 投机发行的存储操作的副本放置在推测性存储缓冲区内。 核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。 当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。 然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。