公开(公告)号：US20250027989A1

公开(公告)日：2025-01-23

申请号：US18354808

申请日：2023-07-19

Applicant: Raytheon Company

Inventor： Micky Harris ,  Magathi J. Willis

IPC: G01R31/28

Abstract: An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.

公开(公告)号：US20250030422A1

公开(公告)日：2025-01-23

申请号：US18353996

申请日：2023-07-18

Applicant: Raytheon Company

Inventor： Micky R. Harris ,  Magathi J. Willis

IPC: H03K19/0185

Abstract: An apparatus includes an input circuit configured to level-shift an input signal and generate an output signal having a voltage range different than a voltage range of the input signal. The input circuit includes (i) a blocking gate configured to level shift the input signal and (ii) an inverter or buffer configured to generate the output signal based on an output of the blocking gate. The input circuit is configured to generate the output signal such that the voltage range of the output signal spans between a first voltage provided to the inverter or buffer and a second voltage provided to the inverter or buffer. The blocking gate may include a transistor, a source or drain of the transistor may be configured to receive the input signal, and a gate of the transistor may be configured to receive the first voltage. The first voltage may include a core voltage of an integrated circuit device.

公开(公告)号：US20250030423A1

公开(公告)日：2025-01-23

申请号：US18354034

申请日：2023-07-18

Applicant: Raytheon Company

Inventor： Micky R. Harris ,  Magathi J. Willis

IPC: H03K19/0185

Abstract: An apparatus includes an output circuit configured to level-shift an incoming signal and generate an output signal having a voltage range different than a voltage range of the incoming signal. The output circuit includes an output driver configured to receive the incoming signal and generate the output signal at a specified voltage level. The output circuit also includes a switched source follower coupled to the output driver. The switched source follower is configured to receive the incoming signal and set the specified voltage level. The switched source follower may include first and second transistors, and the output driver may include a third transistor. The first and third transistors may be configured to be driven by the incoming signal. The second transistor may be configured to be driven by a gate voltage, and the specified voltage level for the output driver may be based on the gate voltage.