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    Digital in-pixel read-out integrated circuit including residue-to-counter calibration
    1.
    发明授权
    Digital in-pixel read-out integrated circuit including residue-to-counter calibration 有权

    公开(公告)号：US10911705B2

    公开(公告)日：2021-02-02

    申请号：US16427968

    申请日：2019-05-31

    Applicant: RAYTHEON COMPANY

    Inventor： Michael J. Batinica ,  Elina R. Glaretas ,  Micky Harris

    IPC: H04N5/3745 ,  H04N5/353 ,  H04N5/378

    Abstract: A digital pixel circuit includes a unit cell configured to accumulate an electrical charge during a frame. The electrical charge is proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell. An image processing unit is in signal communication with the unit cell. The image processing unit is configured to determine a total charge based on a plurality of accumulated charges over a plurality of sequential frames, and to determine an indication of the light intensity of light at the location based on the total charge. The unit cell is configured to operate in a first mode to accumulate the electrical charges over the plurality of sequential frames, and a second mode to perform a calibration operation that calibrates the unit cell based on the electrical charge accumulated during a single frame among the plurality of frames.

    DETECTOR ARRAYS WITH ELECTRONICALLY ADJUSTABLE DETECTOR POSITIONS
    2.
    发明申请
    DETECTOR ARRAYS WITH ELECTRONICALLY ADJUSTABLE DETECTOR POSITIONS 审中-公开
    检测器阵列与电子可调谐探测器位置

    公开(公告)号：US20160331265A1

    公开(公告)日：2016-11-17

    申请号：US14711042

    申请日：2015-05-13

    Applicant: Raytheon Company

    Inventor： Matthew D. Chambers ,  John L. Vampola ,  Micky Harris

    IPC: A61B5/05

    CPC classification number: A61B5/05 ,  A61B5/7203 ,  A61B2562/046 ,  A61B2576/00 ,  H01L27/14856 ,  H04N5/347 ,  H04N5/37206 ,  H04N5/3743

    Abstract: A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.

    Abstract translation: 一种包括被配置为从目标物体接收电磁（EM）辐射的检测器阵列的系统，所述检测器阵列具有一个或多个检测器。 该系统还包括读出集成电路和一个或多个处理器。 读出集成电路具有包括多个检测器边界选择部件的电路，每个检测器边界选择部件中的每一个被配置为从子列边界或可调边界中的至少一个选择或调整检测器边界。

    Anti-blooming buffered direct injection pixels
    4.
    发明授权
    Anti-blooming buffered direct injection pixels 有权

    公开(公告)号：US12203808B1

    公开(公告)日：2025-01-21

    申请号：US18476769

    申请日：2023-09-28

    Applicant: Raytheon Company

    Inventor： Micky Harris ,  Angelo Gregory Scott Gilmore

    IPC: G01J1/44

    Abstract: A pixel disclosed includes an anti-blooming injection transistor (DI) transistor under the control of a BDI amplifier/transistor combination. The “turn on” of the anti-blooming injection transistor is offset from the turn on of the BDI transistor by an offset. When the offset is overcome, excess charge can be diverted (iDiverted) away from an integration capacitor. This can allow the BDI transistor/amplifier combination to hold the detector at nominal bias over an extended range and may reduce blooming. The pixel can be implemented in manner that adds a second transistor and a capacitor to prior BDI designs.

    Digital pixel having high sensitivity and dynamic range
    5.
    发明授权
    Digital pixel having high sensitivity and dynamic range 有权

    公开(公告)号：US11284025B2

    公开(公告)日：2022-03-22

    申请号：US16890483

    申请日：2020-06-02

    Applicant: Raytheon Company

    Inventor： Neil R. Malone ,  Micky Harris ,  Adam M. Kennedy ,  George Paloczi ,  John L. Vampola ,  Christian M. Boemler

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

    PER-PIXEL DETECTOR BIAS CONTROL
    6.
    发明申请
    PER-PIXEL DETECTOR BIAS CONTROL 有权

    公开(公告)号：US20210381888A1

    公开(公告)日：2021-12-09

    申请号：US16892430

    申请日：2020-06-04

    Applicant: RAYTHEON COMPANY

    Inventor： Eric J. Beuville ,  Micky Harris ,  Ryan Boesch ,  Christian M. Boemler

    IPC: G01J1/46 ,  G01J5/34

    Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

    INTERFACE BUILT IN TEST FAILURE DETECTION APPARATUS
    7.
    发明申请
    INTERFACE BUILT IN TEST FAILURE DETECTION APPARATUS 有权

    公开(公告)号：US20250027989A1

    公开(公告)日：2025-01-23

    申请号：US18354808

    申请日：2023-07-19

    Applicant: Raytheon Company

    Inventor： Micky Harris ,  Magathi J. Willis

    IPC: G01R31/28

    Abstract: An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.

    ANTI-BLOOMING BUFFERED DIRECT INJECTION PIXELS
    8.
    发明申请
    ANTI-BLOOMING BUFFERED DIRECT INJECTION PIXELS 有权

    公开(公告)号：US20250027811A1

    公开(公告)日：2025-01-23

    申请号：US18476769

    申请日：2023-09-28

    Applicant: Raytheon Company

    Inventor： Micky Harris ,  Angelo Gregory Scott Gilmore

    IPC: G01J1/44

    Abstract: A pixel disclosed includes an anti-blooming injection transistor (DI) transistor under the control of a BDI amplifier/transistor combination. The “turn on” of the anti-blooming injection transistor is offset from the turn on of the BDI transistor by an offset. When the offset is overcome, excess charge can be diverted (iDiverted) away from an integration capacitor. This can allow the BDI transistor/amplifier combination to hold the detector at nominal bias over an extended range and may reduce blooming. The pixel can be implemented in manner that adds a second transistor and a capacitor to prior BDI designs.

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