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公开(公告)号：US08805296B2
公开(公告)日：2014-08-12
申请号：US13358895
申请日：2012-01-26
IPC分类号： H04B1/38
CPC分类号： H04B1/006
摘要： A transceiver circuit includes: a transmit path with at least one of each of a digital to analog converter converting a digital input signal to an analog signal, a filter, a first frequency synthesizer, a mixer to produce an RF output, and an amplifier amplifying the RF output for transmission; and a receive path with at least one of each of a second amplifier amplifying a received RF input, a second frequency synthesizer, a second mixer to produce a baseband signal, a second filter, and an analog to digital converter converting the baseband signal to a digital output signal; at least one switch selectively connecting different points of the circuit thereby to bypass at least one component of the circuit; and a control input connected to the switch to receive control signals for controlling operation of the switch.
摘要翻译： 收发器电路包括：具有将数字输入信号转换为模拟信号的数模转换器中的至少一个的传输路径，滤波器，第一频率合成器，混频器以产生RF输出，以及放大器放大 射频输出用于传输; 以及具有放大接收的RF输入的第二放大器的每一个中的至少一个的接收路径，第二频率合成器，第二混频器以产生基带信号，第二滤波器和将基带信号转换为 数字输出信号; 至少一个开关选择性地连接电路的不同点，从而绕过电路的至少一个部件; 以及连接到开关的控制输入端，以接收用于控制开关操作的控制信号。
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公开(公告)号：US20130195151A1
公开(公告)日：2013-08-01
申请号：US13358895
申请日：2012-01-26
IPC分类号： H04B1/38
CPC分类号： H04B1/006
摘要： A transceiver circuit comprising a transmit path and a receive path, the transmit path comprising at least one digital to analogue converter for converting a digital input signal to an analogue signal, at least one filter for filtering the analogue signal, at least one first frequency synthesizer for producing a first synthesized RF signal, at least one mixer for mixing the analogue signal with the RF signal to produce an RF output, and at least one amplifier for amplifying the RF output for transmission; and the receive path comprising at least one second amplifier for amplifying a received RF input, at least one second frequency synthesizer for generating a second synthesized RF signal, at least one second mixer for mixing the amplified RF input with the second synthesized RF signal to produce a baseband signal, at least one second filter for filtering the baseband signal, and at least one analogue to digital converter for converting the baseband signal to a digital output signal, at least one switch arranged to selectively connect together different points of the circuit thereby to bypass at least one component of the circuit and a control input connected to the at least one switch and arranged to receive control signals for controlling operation of the at least one switch.
摘要翻译： 一种包括发射路径和接收路径的收发器电路，所述发射路径包括用于将数字输入信号转换成模拟信号的至少一个数模转换器，用于滤波模拟信号的至少一个滤波器，至少一个第一频率合成器 用于产生第一合成RF信号的至少一个混频器，用于将模拟信号与RF信号混合以产生RF输出的至少一个混频器，以及用于放大RF输出以供传输的至少一个放大器; 并且所述接收路径包括用于放大接收的RF输入的至少一个第二放大器，用于产生第二合成RF信号的至少一个第二频率合成器，用于将放大的RF输入与第二合成RF信号混合的至少一个第二混频器，以产生 基带信号，用于滤波基带信号的至少一个第二滤波器，以及用于将基带信号转换为数字输出信号的至少一个模数转换器，布置成选择性地将电路的不同点连接在一起的至少一个开关， 绕过所述电路的至少一个部件和连接到所述至少一个开关的控制输入，并被布置成接收用于控制所述至少一个开关的操作的控制信号。
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公开(公告)号：US06825887B2
公开(公告)日：2004-11-30
申请号：US09886314
申请日：2001-06-21
IPC分类号： H04N964
CPC分类号： H04N9/72
摘要： An interface circuit 13 is provided for a display apparatus 3 such as a television. The display apparatus 3 comprises a video signal processing circuit 8 for processing a composite video signal to derive color component signals having variable black and white levels; a linear amplifier 10 for amplifying the color component signals; and a display device 4 such as a CRT driven by the output of the linear amplifier 10. The interface circuit 13 is provided to interface the color component signals with a digital signal processor 14. The interface circuit 13 includes a modification circuit 22 arranged to perform a modification of voltage levels of the color component signals and to output the modified color component signals to the digital signal processor 14 via an A/D convertor 18. The interface circuit 13 further includes a remodification circuit 23 arranged to receive processed color component signals supplied from the digital signal processor 14 via a D/A convertor 19 and to perform a modification of the processed color component signals which is the inverse of the modification performed by the modification circuit 22. The modification and remodification circuits 22, 23 use calibration signals including the black and white levels of the color component signals inserted in a predetermined period in the vertical blanking interval of the color component signal. The interface circuit 13 reduces the resolution necessary in the A/D convertor 18.
摘要翻译： 为电视机等显示装置3提供接口电路13。 显示装置3包括视频信号处理电路8，用于处理复合视频信号以导出具有可变黑白电平的色分量信号; 用于放大色分量信号的线性放大器10; 以及由线性放大器10的输出驱动的诸如CRT的显示装置4.接口电路13用于将彩色分量信号与数字信号处理器14进行接口。接口电路13包括：修改电路22，用于执行 修改颜色分量信号的电压电平，并经由A / D转换器18将经修改的颜色分量信号输出到数字信号处理器14.接口电路13还包括再编码电路23，其被配置为接收所提供的经处理的颜色分量信号 从数字信号处理器14通过D / A转换器19进行处理的颜色分量信号的修改，这是由修改电路22执行的修改的倒数。修改和再变换电路22,23使用校准信号，包括 颜色分量信号的黑白电平在垂直布局中以预定时段插入 颜色分量信号的间隔时间。 接口电路13降低了A / D转换器18中所需的分辨率。
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公开(公告)号：US07808287B2
公开(公告)日：2010-10-05
申请号：US12161945
申请日：2007-01-15
申请人： Robin James Miller
发明人： Robin James Miller
IPC分类号： H03K25/00
CPC分类号： H03K23/544 , G06F1/3203 , G06F1/3287 , H03F3/189 , H03F3/45188 , H03F2200/294 , H03F2200/372 , H03F2200/489 , H03F2200/492 , Y02D10/126 , Y02D10/171
摘要： A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.
摘要翻译： 一种用于从输入时钟信号导出输出时钟信号的电路，所述输出时钟信号的频率是所述输入时钟信号的频率的1 / N，其中N是奇数。 电路包括被配置为锁存环的多个锁存器，锁存器被连续地对配置，每对锁存器包括第一锁存器，其中第一锁存器接通输入时钟信号的上升沿或下降沿之一，以及第二锁存器， 打开输入时钟信号的上升沿或下降沿的另一个。 RS触发器被耦合以在其设置和复位输入中的一个处接收来自在上升沿上接通的锁存环的输出，并且在另一个设置和复位输入处，来自锁存环的输出被接通 一个下降的边缘。 所述输出时钟信号被提供在RS触发器的输出处。
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公开(公告)号：US20090251176A1
公开(公告)日：2009-10-08
申请号：US12161945
申请日：2007-01-15
申请人： Robin James Miller
发明人： Robin James Miller
IPC分类号： H03K21/00
CPC分类号： H03K23/544 , G06F1/3203 , G06F1/3287 , H03F3/189 , H03F3/45188 , H03F2200/294 , H03F2200/372 , H03F2200/489 , H03F2200/492 , Y02D10/126 , Y02D10/171
摘要： A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.
摘要翻译： 一种用于从输入时钟信号导出输出时钟信号的电路，所述输出时钟信号的频率是所述输入时钟信号的频率的1 / N，其中N是奇数。 电路包括被配置为锁存环的多个锁存器，锁存器被连续地对配置，每对锁存器包括第一锁存器，其中第一锁存器接通输入时钟信号的上升沿或下降沿之一，以及第二锁存器， 打开输入时钟信号的上升沿或下降沿的另一个。 RS触发器被耦合以在其设置和复位输入中的一个处接收来自在上升沿上接通的锁存环的输出，并且在另一个设置和复位输入处，来自锁存环的输出被接通 一个下降的边缘。 所述输出时钟信号被提供在RS触发器的输出处。
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