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1.发明公开公开(公告)号：US20240146272A1
公开(公告)日：2024-05-02
申请号：US18406064
申请日：2024-01-05
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
CPC分类号： H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G3/3052 , H03G2201/504
摘要： An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号：US11870405B2
公开(公告)日：2024-01-09
申请号：US17503710
申请日：2021-10-18
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
CPC分类号： H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G3/3052 , H03G2201/504
摘要： An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号：US11664769B2
公开(公告)日：2023-05-30
申请号：US17843372
申请日：2022-06-17
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US20190245497A1
公开(公告)日：2019-08-08
申请号：US15887816
申请日：2018-02-02
申请人： pSemi Corporation
发明人： Miles Sanner , Emre Ayranci
CPC分类号： H03F3/195 , H03F1/0211 , H03F1/223 , H03F1/56 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/111 , H03F2200/222 , H03F2200/231 , H03F2200/249 , H03F2200/267 , H03F2200/294 , H03F2200/387 , H03F2200/391 , H03F2200/396 , H03F2200/421 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2203/7209 , H04B1/16
摘要： A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
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公开(公告)号：US20180248530A1
公开(公告)日：2018-08-30
申请号：US15691788
申请日：2017-08-31
发明人： Maomi Katsumata
CPC分类号： H03G3/3042 , H01L23/66 , H01L27/1203 , H01L2223/665 , H03F1/0211 , H03F1/0261 , H03F1/223 , H03F1/301 , H03F3/193 , H03F3/21 , H03F3/245 , H03F3/45183 , H03F2200/18 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03G1/0029 , H03G1/007 , H03G3/3052
摘要： A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.
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公开(公告)号：US20180198422A1
公开(公告)日：2018-07-12
申请号：US15916411
申请日：2018-03-09
发明人： Pete Sivonen , Jarkko Jussila , Sami Vilhonen
CPC分类号： H03F1/56 , H03F1/223 , H03F1/26 , H03F3/193 , H03F3/265 , H03F2200/222 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03F2200/489 , H03F2200/54 , H03F2200/87 , H04B1/1036
摘要： An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.
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公开(公告)号：US20180175803A1
公开(公告)日：2018-06-21
申请号：US15896844
申请日：2018-02-14
CPC分类号： H03F1/223 , H01L27/0255 , H02H9/046 , H03F1/523 , H03F3/193 , H03F2200/489
摘要： An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.
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公开(公告)号：US20180083579A1
公开(公告)日：2018-03-22
申请号：US15272103
申请日：2016-09-21
发明人： Hossein Noori , Chih-Chieh Cheng
CPC分类号： H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US20170230014A1
公开(公告)日：2017-08-10
申请号：US15229464
申请日：2016-08-05
发明人： Raphael Paulin
CPC分类号： H03F1/565 , H03F1/086 , H03F1/223 , H03F3/195 , H03F2200/108 , H03F2200/181 , H03F2200/216 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/321 , H03F2200/336 , H03F2200/387 , H03F2200/391 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/75 , H04B5/0081
摘要： A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
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公开(公告)号：US09712195B2
公开(公告)日：2017-07-18
申请号：US14711623
申请日：2015-05-13
发明人： Cheng-Han Wang , Conor Donovan , Jesse Aaron Richmond , Jin-Su Ko
IPC分类号： H04B1/40 , H04B1/10 , H03F3/19 , H03F3/21 , H04B1/3827 , H04B1/48 , H03F1/56 , H03F1/22 , H03F1/34 , H03F3/193 , H03F3/24
CPC分类号： H04B1/1027 , H03F1/223 , H03F1/347 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H04B1/0458 , H04B1/3827 , H04B1/48 , H04B2001/0408 , H04B2001/1072 , H04B2001/485
摘要： An amplifier includes a gain transistor including a control terminal to receive an input signal. A degeneration inductor is coupled between the first terminal of the gain transistor and ground. A shunt inductor and a capacitor are coupled in series between the control terminal of the gain transistor and ground, and form a filter to attenuate frequencies of the input signal within a frequency range. The degeneration inductor and the shunt inductor form a transformer to provide impedance matching.
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