公开(公告)号：US20240331626A1

公开(公告)日：2024-10-03

申请号：US18535968

申请日：2023-12-11

Applicant: Samsung Display Co., Ltd.

Inventor： HAE-KWAN SEO ,  BON-SEOG GU ,  JIYOUN KIM ,  JINYOUNG ROH ,  JAEKEUN LIM

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0257 ,  G09G2320/0666 ,  G09G2330/021

Abstract: A display panel is disclosed that includes 2-1 to 2-4 pixel circuit sequentially disposed in a first direction in a second pixel row and 2-1 to 2-4 light emitting area sequentially disposed in the first direction. The 2-1 pixel circuit is connected to a first data line, the 2-2 pixel circuit is connected to a second data line, the 2-3 pixel circuit is connected to a third data line and the 2-4 pixel circuit is connected to a fourth data line. The 2-1 pixel circuit is connected to the 2-3 light emitting area, the 2-2 pixel circuit is connected to the 2-1 light emitting area, the 2-3 pixel circuit is connected to the 2-2 light emitting area and the 2-4 pixel circuit is connected to the 2-4 light emitting area. A color of the 2-1 light emitting area is different from a color of the 2-3 light emitting area.

公开(公告)号：US20230419882A1

公开(公告)日：2023-12-28

申请号：US18142237

申请日：2023-05-02

Applicant: Samsung Display Co., LTD.

Inventor： JAEKEUN LIM ,  BON-SEOG GU ,  SANGAN KWON ,  SOON-DONG KIM ,  JINYOUNG ROH ,  HAE-KWAN SEO

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0852 ,  G09G2300/0819 ,  G09G2320/0233 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2310/0202

Abstract: A display device includes a display panel including a pixel including a pixel circuit and a light emitting element, a plurality of scan lines connected to the pixel circuit, an emission control line connected to the pixel circuit, and a data line connected to the pixel circuit. The pixel circuit includes a first capacitor connected to a first node and a second node opposite to the first node, a first circuit portion that includes a first transistor connected between the data line and the first node and a second transistor connected between the first transistor and the first node, and a second circuit portion connected to the second node and the light emitting element. Before the light emitting element emits light, a reference voltage is provided to a third node between the first transistor and the second transistor.

公开(公告)号：US20220366828A1

公开(公告)日：2022-11-17

申请号：US17645081

申请日：2021-12-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SEHYUK PARK ,  JINYOUNG ROH ,  WOOMI BAE ,  HAE-KWAN SEO ,  YOUNGHA SOHN ,  JIN-WOOK YANG

IPC: G09G3/20

Abstract: A display device includes four pixel arrays, a data driver, and a demultiplexer. The data driver is electrically connected to first and second data output lines. The demultiplexer electrically connects first and second data lines to the first data output line and electrically connects third and fourth data lines to the second data output line. The first to fourth pixel arrays are adjacent to the first to fourth data lines, respectively. Each of the first to fourth pixel arrays includes first and second color pixels. The first color pixels in the second pixel array are connected to the second data line, the second color pixels in the second pixel array are connected to the third data line, the second color pixels in the third pixel array are connected to the third data line, and the first color pixels in the third pixel array are connected to the second data line.

公开(公告)号：US20220238074A1

公开(公告)日：2022-07-28

申请号：US17717997

申请日：2022-04-11

Applicant: Samsung Display Co., Ltd.

Inventor： SEHYUK PARK ,  HONGSOO KIM ,  JINYOUNG ROH ,  BONGHYUN YOU ,  HYOJIN LEE ,  JAEKEUN LIM

IPC: G09G3/3266 ,  G09G3/3275

Abstract: A display apparatus includes a display panel, a gate driver, a data driver, a driving controller and a power voltage generator. The display panel displays an image based on input image data. The gate driver outputs a gate signal to a gate line. The data driver outputs a data voltage to a data line. The driving controller drives display areas of the display panel in different driving frequencies. The power voltage generator outputs a data power voltage to the data driver. The driving controller outputs an output data enable signal including a writing period having an active signal and a holding period having an inactive signal for the respective display areas. The power voltage generator generates the data power voltage having a high power voltage level during the writing period and a low power voltage level in at least a portion of the holding period.

公开(公告)号：US20220013059A1

公开(公告)日：2022-01-13

申请号：US17212392

申请日：2021-03-25

Applicant: Samsung Display Co., Ltd.

Inventor： SEHYUK PARK ,  HONGSOO KIM ,  JINYOUNG ROH ,  HYOJIN LEE ,  JAEKEUN LIM

IPC: G09G3/20

Abstract: A display apparatus includes a display panel, a data driver and a frequency controller. The display panel displays an image based on an input image data. The data driver outputs a data voltage to the display panel. The frequency controller determines a driving frequency of the display panel based on the input image data and a play speed setting.

公开(公告)号：US20240221613A1

公开(公告)日：2024-07-04

申请号：US18227975

申请日：2023-07-31

Applicant: Samsung Display Co., Ltd.

Inventor： JINYOUNG ROH ,  HAE-KWAN SEO ,  BON-SEOG GU ,  JAEKEUN LIM

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021

Abstract: A display panel of a display device includes first and second pixel circuits disposed in a first row and connected to 0-th and second data lines, respectively, third and fourth pixel circuits disposed in a second row and connected to first and third data lines, respectively, a first light-emitting area connected to the first pixel circuit via a first connection wiring, a second light-emitting area at least partially overlapping the second pixel circuit and connected to the second pixel circuit, a third light-emitting area at least partially overlapping the third pixel circuit and connected to the third pixel circuit, and a fourth light-emitting area connected to the fourth pixel circuit via a second connection wiring.

公开(公告)号：US20240196677A1

公开(公告)日：2024-06-13

申请号：US18510659

申请日：2023-11-16

Applicant: Samsung Display Co., Ltd.

Inventor： JAEKEUN LIM ,  BON-SEOG GU ,  JINYOUNG ROH ,  HAE-KWAN SEO

IPC: H10K59/131 ,  G09G3/3233

CPC classification number: H10K59/131 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2330/021

Abstract: Disclosed is a display device including a display panel that includes a first area and a second area. The second area is divided into a first side area and a second side area around a central axis. The display panel includes a first side normal pixel disposed in each of first and second rows of the first side area, a first side non-normal pixel disposed in the second row among the first and second rows of the first side area, a second side normal pixel disposed in each of first and second rows of the second side area, and a second side non-normal pixel disposed in the first row among the first and second rows of the second side area. Each of the first side non-normal pixel and the second side non-normal pixel further includes a connection wiring connecting a data line and a pixel circuit to each other.

公开(公告)号：US20240185752A1

公开(公告)日：2024-06-06

申请号：US18442589

申请日：2024-02-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SEHYUK PARK ,  JINYOUNG ROH ,  WOOMI BAE ,  HAE-KWAN SEO ,  YOUNGHA SOHN ,  JIN-WOOK YANG

IPC: G09G3/20

CPC classification number: G09G3/2003 ,  G09G2300/0452 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/021

Abstract: A display device includes four pixel arrays, a data driver, and a demultiplexer. The data driver is electrically connected to first and second data output lines. The demultiplexer electrically connects first and second data lines to the first data output line and electrically connects third and fourth data lines to the second data output line. The first to fourth pixel arrays are adjacent to the first to fourth data lines, respectively. Each of the first to fourth pixel arrays includes first and second color pixels. The first color pixels in the second pixel array are connected to the second data line, the second color pixels in the second pixel array are connected to the third data line, the second color pixels in the third pixel array are connected to the third data line, and the first color pixels in the third pixel array are connected to the second data line.

公开(公告)号：US20230065185A1

公开(公告)日：2023-03-02

申请号：US17863519

申请日：2022-07-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYOJIN LEE ,  WOOMI BAE ,  HUI NAM ,  JINYOUNG ROH ,  SEHYUK PARK ,  JAEKEUN LIM

IPC: G09G3/3266

Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver which drives the display panel. The panel driver determines whether input image data represents a still image. When the input image data represents the still image, the panel driver determines a flicker value of the still image, applies a compensation value corresponding to a carry shift interval to the flicker value, determines a driving frequency for the display panel based on the flicker value to which the compensation value is applied, and performs an alternate driving operation for the display panel at the driving frequency.

公开(公告)号：US20220059039A1

公开(公告)日：2022-02-24

申请号：US17389466

申请日：2021-07-30

Applicant: Samsung Display Co., Ltd.

Inventor： JINYOUNG ROH ,  HONGSOO KIM ,  SEHYUK PARK ,  HYOJIN LEE ,  JAEKEUN LIM

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driver includes a first stage, a second stage, a third stage and a fourth stage. The first stage includes a first clock terminal receiving a first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal and an output terminal outputting a first gate output signal. The second stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the vertical start signal and an output terminal outputting a second gate output signal. The third stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the first gate output signal and an output terminal outputting a third gate output signal.