公开(公告)号：US20150357245A1

公开(公告)日：2015-12-10

申请号：US14830199

申请日：2015-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon JEONG ,  Jae Yup CHUNG ,  Heesoo KANG ,  Donghyun KIM ,  Sanghyuk HONG ,  Soohun HONG

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Abstract translation: 半导体器件包括具有短边和短边的鳍片区域，第一场绝缘层，其包括比翅片区域低的顶表面，并且与鳍片区域的短边的侧表面相邻;第二场绝缘层，包括 与翅片区域相比较靠近散热片区域的长边侧表面的顶表面，第一场绝缘层上的蚀刻阻挡图案，鳍状区域上的第一栅极和第二场绝缘层， 面对翅片区域的顶表面和翅片区域的长边的侧表面。 第二栅极位于与第一场绝缘层重叠的蚀刻阻挡图案上。 源极/漏极区在第一栅极和第二栅极之间，与蚀刻阻挡图案接触。

公开(公告)号：US20190074223A1

公开(公告)日：2019-03-07

申请号：US16183245

申请日：2018-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon JEONG ,  Jae Yup CHUNG ,  Heesoo KANG ,  Donghyun KIM ,  Sanghyuk HONG ,  Soohun HONG

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US20170365523A1

公开(公告)日：2017-12-21

申请号：US15674185

申请日：2017-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon JEONG ,  Jae Yup CHUNG ,  Heesoo KANG ,  Donghyun KIM ,  Sanghyuk HONG ,  Soohun HONG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US20190067287A1

公开(公告)日：2019-02-28

申请号：US16176179

申请日：2018-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.