公开(公告)号：US20190067287A1

公开(公告)日：2019-02-28

申请号：US16176179

申请日：2018-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.