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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240284662A1

    公开(公告)日：2024-08-22

    申请号：US18435231

    申请日：2024-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heejae CHAE ,  Taejin PARK ,  Hyunjin LEE ,  Hosang LEE ,  Yun CHOI

    IPC: H10B12/00 ,  H01L21/762 ,  H01L29/49

    CPC classification number: H10B12/488 ,  H01L21/76232 ,  H01L29/4916 ,  H10B12/34

    Abstract: A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240341089A1

    公开(公告)日：2024-10-10

    申请号：US18474699

    申请日：2023-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hosang LEE ,  Taejin PARK ,  Hyunjin LEE ,  Heejae CHAE ,  Yun CHOI

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/482

    Abstract: A semiconductor device according to some example embodiments includes: a substrate that includes an active region between element isolation layers; a word line that overlaps the active region and extends in a first direction; a bit line that overlaps the active region and extends in a second direction crossing the first direction; a buried contact connected to the active region; a first pad between and connecting the active region and the bit line; a second pad between and connecting the active region and the buried contact; and a landing pad connected to the buried contact. Each of the element isolation layers includes a first element isolation layer and a second element isolation layer inside the first element isolation layer, and each of the first pad and the second pad are between the element isolation layers.

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