SUBSTRATE DEBONDING APPARATUS
    1.
    发明申请

    公开(公告)号:US20210358778A1

    公开(公告)日:2021-11-18

    申请号:US17078190

    申请日:2020-10-23

    Abstract: A substrate debonding apparatus configured to separate a support substrate attached to a first surface of a device substrate by an adhesive layer, the substrate debonding apparatus including a substrate chuck configured to support a second surface of the device substrate, the second surface being opposite to the first surface of the device substrate; a light irradiator configured to irradiate light to an inside of the adhesive layer; and a mask between the substrate chuck and the light irradiator, the mask including an opening through which an upper portion of the support substrate is exposed, and a first cooling passage or a second cooling passage, the first cooling passage being configured to provide a path in which a coolant is flowable, the second cooling passage being configured to provide a path in which air is flowable and to provide part of the air to a central portion of the opening.

    SEMICONDUCTOR PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING SEMICONDUCTOR PROCESSING APPARATUS

    公开(公告)号:US20240282604A1

    公开(公告)日:2024-08-22

    申请号:US18439813

    申请日:2024-02-13

    CPC classification number: H01L21/6715 H01L21/67288 H01L22/20

    Abstract: A method of manufacturing a semiconductor device includes: performing a first semiconductor process on a semiconductor wafer including a front side and a back side opposing the front side; loading the semiconductor wafer into a semiconductor processing apparatus including a support, a spraying apparatus, and a warpage measuring apparatus, wherein the semiconductor wafer is supported by the support, wherein the spraying apparatus is disposed below the semiconductor wafer, and the warpage measuring apparatus is an apparatus configured to measure warpage of the semiconductor wafer; forming a warpage compensation pattern on the back side of the semiconductor wafer using the spraying apparatus until a warpage measurement value of the semiconductor wafer is within a predetermined range, while measuring warpage of the semiconductor wafer using the warpage measuring apparatus; and unloading, from the semiconductor processing apparatus, the semiconductor wafer on which the warpage compensation pattern is formed.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20240341089A1

    公开(公告)日:2024-10-10

    申请号:US18474699

    申请日:2023-09-26

    CPC classification number: H10B12/485 H10B12/02 H10B12/482

    Abstract: A semiconductor device according to some example embodiments includes: a substrate that includes an active region between element isolation layers; a word line that overlaps the active region and extends in a first direction; a bit line that overlaps the active region and extends in a second direction crossing the first direction; a buried contact connected to the active region; a first pad between and connecting the active region and the bit line; a second pad between and connecting the active region and the buried contact; and a landing pad connected to the buried contact. Each of the element isolation layers includes a first element isolation layer and a second element isolation layer inside the first element isolation layer, and each of the first pad and the second pad are between the element isolation layers.

    SEMICONDUCTOR DEVICE
    4.
    发明申请

    公开(公告)号:US20250016994A1

    公开(公告)日:2025-01-09

    申请号:US18668431

    申请日:2024-05-20

    Abstract: The semiconductor includes a substrate including first active patterns, the substrate defining trenches between the first active patterns; an upper silicon pattern on an upper sidewall of at least a portion of each of the first active patterns; and a first contact plug contacting an edge portion in a longitudinal direction of each of the first active patterns, a sidewall of the first contact plug contacting at least a portion of the upper silicon pattern, and the first contact plug having a bottom lower than a bottom of the upper silicon pattern.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

    公开(公告)号:US20240284662A1

    公开(公告)日:2024-08-22

    申请号:US18435231

    申请日:2024-02-07

    CPC classification number: H10B12/488 H01L21/76232 H01L29/4916 H10B12/34

    Abstract: A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.

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