公开(公告)号：US20200243374A1

公开(公告)日：2020-07-30

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon CHOI ,  Jaeung KOO ,  Kwansung KIM ,  Bo Yun KIM ,  Wandon KIM ,  Boun YOON ,  Jeonghyuk YIM ,  Yeryung JEON

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US20180166343A1

公开(公告)日：2018-06-14

申请号：US15646300

申请日：2017-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ho BAE ,  Jaeseok KIM ,  Hoyoung KIM ,  Boun YOON ,  KyungTae LEE ,  Kwansung KIM ,  Eunji PARK

IPC: H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.