公开(公告)号：US20220139474A1

公开(公告)日：2022-05-05

申请号：US17384219

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEJI LEE ,  RAEYOUNG LEE ,  JINKYU KANG ,  SEJUN PARK ,  JAEDUK LEE

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

公开(公告)号：US20230023911A1

公开(公告)日：2023-01-26

申请号：US17867962

申请日：2022-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEDUK LEE ,  JOONAM KIM ,  SEJUN PARK ,  RAEYOUNG LEE

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Semiconductor devices are provided. The semiconductor devices may include a peripheral circuit structure, a memory cell block arranged on the peripheral circuit structure and including strings, each of which includes a lower select transistor, memory cell transistors, and an upper select transistor connected in series and stacked in a vertical direction, and bit lines on the memory cell block. The bit lines may include a first bit line electrically connected to first to third strings of the strings. The lower select transistors of the first to third strings include first to third lower select gate electrodes, respectively. The second lower select gate electrode may be arranged at a different vertical level from the first lower select gate electrode, and the third lower select gate electrode may be arranged at the same vertical level as the first lower select gate electrode.