公开(公告)号：US20240038843A1

公开(公告)日：2024-02-01

申请号：US18378710

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin JEONG ,  Sunwook KIM ,  Junbeom PARK ,  Seungmin SONG

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/7854

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US20230178606A1

公开(公告)日：2023-06-08

申请号：US18096663

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin JEONG ,  Sunwook KIM ,  Junbeom PARK ,  Seungmin SONG

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/7854

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US20210305371A1

公开(公告)日：2021-09-30

申请号：US17345241

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin JEONG ,  Sunwook KIM ,  Junbeom PARK ,  Seungmin SONG

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US20230184830A1

公开(公告)日：2023-06-15

申请号：US17988989

申请日：2022-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwook KIM ,  Heeseong LEE ,  Myonghoon YANG ,  Manhwee JO ,  Wooil KIM

IPC: G01R31/317

CPC classification number: G01R31/31718 ,  G01R31/31723 ,  G01R31/31712

Abstract: A system of monitoring performance of an electronic device including: a plurality of performance monitoring circuits included in an electronic device, wherein the plurality of performance monitoring circuits are configured to generate a plurality of monitor output signals including performance data of the electronic device; a monitoring bus configured to receive the plurality of monitor output signals and generate a. bus output signal by interleaving the performance data included in the plurality of monitor output signals; and an embedded trace router configured to receive the bus output signal and store, in a memory device included in the electronic device, the performance data. included in the bus output signal,