公开(公告)号：US20150243353A1

公开(公告)日：2015-08-27

申请号：US14505523

申请日：2014-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGKYU LEE ,  YEONGTAEK LEE ,  YOUNGBAE KIM

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

Abstract: A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.

Abstract translation: 一种在非易失性存储器件中复位可变电阻存储单元的方法包括： 使用相应的顺应性电流将存储器单元编程为设定状态，然后通过预读可变电阻存储单元来确定其电阻并使用响应中确定的可变复位电压来复位存储单元来将存储单元编程为复位状态 到确定的阻力。

公开(公告)号：US20150243355A1

公开(公告)日：2015-08-27

申请号：US14532105

申请日：2014-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGKYU LEE ,  YEONGTAEK LEE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5614 ,  G11C11/5685

Abstract: A method is provided for programming a nonvolatile memory device comprising a variable resistance memory cell connected to a bitline and a wordline. The method comprises precharging the bitline to a first bias voltage, precharging the wordline to a second bias voltage, wherein a voltage difference between the first bias voltage and the second bias voltage is less than a threshold voltage of the memory cell, and applying a first write voltage to the bitline and a second write voltage to the wordline in response to a select signal, wherein a voltage difference between the first write voltage and the second write voltage is greater than the threshold voltage.

Abstract translation: 提供一种用于对包括连接到位线和字线的可变电阻存储器单元的非易失性存储器件进行编程的方法。 该方法包括将位线预充电到第一偏置电压，将字线预充电到第二偏置电压，其中第一偏置电压和第二偏置电压之间的电压差小于存储器单元的阈值电压，并且施加第一偏置电压 向所述位线写入电压，并响应于选择信号向所述字线施加第二写入电压，其中所述第一写入电压和所述第二写入电压之间的电压差大于所述阈值电压。

公开(公告)号：US20220416076A1

公开(公告)日：2022-12-29

申请号：US17580717

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYONGSIK YEOM ,  YOUNGCHEON JEONG ,  YONGKYU LEE

IPC: H01L29/788 ,  H01L27/11524 ,  H01L29/66 ,  H01L27/11529 ,  H01L29/423

Abstract: An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

公开(公告)号：US20210391000A1

公开(公告)日：2021-12-16

申请号：US17147557

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOO-WOONG LEE ,  DOO-HO CHO ,  SANG SOO PARK ,  YONGKYU LEE

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4074

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array that includes a plurality of memory cells, a page buffer circuit that is connected with the memory cell array through a plurality of bit lines and performs a sensing operation of sensing memory cells selected from the plurality of memory cells through the plurality of bit lines during a sensing time, an input/output circuit that performs a data output operation of outputting data from the page buffer circuit to an external device through data lines, and a sensing time control circuit that adjusts the sensing time when the data output operation is performed during the sensing time.