公开(公告)号：US20140247646A1

公开(公告)日：2014-09-04

申请号：US14171873

申请日：2014-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KWON ,  Hoi-Ju CHUNG ,  Chae-Hoon KIM ,  Yong-Jin KWON ,  Eun-Hye PARK ,  Yong-Jun LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2213/72

Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。