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    Multi-step pre-read for write operations in memory devices
    1.
    发明授权
    Multi-step pre-read for write operations in memory devices 有权

    公开(公告)号：US12106803B2

    公开(公告)日：2024-10-01

    申请号：US17824776

    申请日：2022-05-25

    申请人： Micron Technology, Inc.

    发明人： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

    IPC分类号： G11C11/4074 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0076

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

    Read reference current generator
    4.
    发明授权
    Read reference current generator 有权

    公开(公告)号：US12057163B2

    公开(公告)日：2024-08-06

    申请号：US17824818

    申请日：2022-05-25

    申请人： Samsung Electronics Co., Ltd.

    发明人： Antonyan Artur ,  Jieun Kim

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0026

    摘要： A read reference current generator includes a temperature coefficient (TC) controller configured to adjust a temperature coefficient in response to a first control signal and generate a read reference current having an adjusted temperature coefficient, a plurality of replica circuits configured to receive the read reference current and adjust an absolute value of the read reference current with different scale factors to generate a plurality of branch currents, and a plurality of switches configured to control connection of the TC controller and the plurality of replica circuits in response to a second control signal, wherein an equivalent resistance value of each of the plurality of replica circuits corresponds to a multiple of an equivalent resistance value of a data read path, and the data read path includes a selected memory cell and a clamping circuit clamping a voltage level of a selected bit line to a determined value.

    Voltage regulator circuit for a switching circuit load
    5.
    发明授权
    Voltage regulator circuit for a switching circuit load 有权

    公开(公告)号：US12046987B2

    公开(公告)日：2024-07-23

    申请号：US17582431

    申请日：2022-01-24

    申请人： STMicroelectronics S.r.l.

    发明人： Marco Pasotti ,  Laura Capecchi ,  Riccardo Zurla ,  Marcella Carissimi

    IPC分类号： H02M3/07 ,  G05F1/575 ,  H02M1/00 ,  G11C13/00

    CPC分类号： H02M1/0045 ,  G05F1/575 ,  H02M3/073 ,  G11C13/0004 ,  G11C13/0038

    摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.

    Write error counter for media management in a memory device
    6.
    发明授权
    Write error counter for media management in a memory device 有权

    公开(公告)号：US12014775B2

    公开(公告)日：2024-06-18

    申请号：US17732353

    申请日：2022-04-28

    申请人： Micron Technology, Inc.

    发明人： John Christopher M. Sancon

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0035 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes a sense amplifier, a counter, and memory having memory cells. Access lines are used to select the memory cells for performing write operations. The memory device includes a controller to control the applying of a voltage to the memory cell. The voltage is applied during a write operation using the access lines. The sense amplifier is used to determine whether the memory cell reaches a threshold state or snaps. In response to determining that the memory cell does not snap, a write error count is incremented using the counter. The controller reads the counter to determine the write error count, and based on the write error count, the controller performs one or more media management or memory device control actions.

    Refresh of neighboring memory cells based on read status
    8.
    发明授权
    Refresh of neighboring memory cells based on read status 有权

    公开(公告)号：US12009027B2

    公开(公告)日：2024-06-11

    申请号：US17561340

    申请日：2021-12-23

    申请人： Micron Technology, Inc.

    发明人： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

    IPC分类号： G11C13/00 ,  G11C11/56

    CPC分类号： G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C11/5678

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.