公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

公开(公告)号：US20240088219A1

公开(公告)日：2024-03-14

申请号：US18452858

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pilkwang KIM ,  Seunghyun SONG ,  Yoonsuk KIM ,  Gwangjun KIM ,  Jaemin KIM

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.