公开(公告)号：US11756877B2

公开(公告)日：2023-09-12

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Ohsawa ,  Kota Funayama ,  Hisaya Sakai ,  Yoshitaka Otsu

IPC: H01L23/52 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

公开(公告)号：US12185542B2

公开(公告)日：2024-12-31

申请号：US17654465

申请日：2022-03-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Ohsawa

IPC: H10B43/27 ,  G11C11/22 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. Stepped surfaces including vertical sidewalls of the insulating layers are present in a staircase region. Pad stacks are located on the stepped surfaces. Each of the pad stacks includes an insulating pad having a same material composition as the insulating layers, and a dielectric material pad having a different material composition than the insulating layers and having sidewalls that are vertically coincident with sidewalls of the insulating pad. Memory stack structures extend through the alternating stack. Each of the memory stack structures includes a vertical stack of memory elements and a vertical semiconductor channel.