公开(公告)号：US10910069B2

公开(公告)日：2021-02-02

申请号：US16909821

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US20200321060A1

公开(公告)日：2020-10-08

申请号：US16909821

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US20200098434A1

公开(公告)日：2020-03-26

申请号：US16142386

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US10726925B2

公开(公告)日：2020-07-28

申请号：US16142386

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.