公开(公告)号：US12213320B2

公开(公告)日：2025-01-28

申请号：US17328302

申请日：2021-05-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji Shimabukuro ,  Takashi Yamaha

IPC: H10B43/50 ,  H01L21/768 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20 ,  H10B51/50 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through a first region of the alternating stack, memory opening fill structures located in the memory openings, and support pillar structures vertically extending through a second region of the alternating stack. Each of the support pillar structures includes a central columnar structure and a set of fins laterally protruding from the central columnar structure at levels of a subset of the electrically conductive layers.

公开(公告)号：US10797035B1

公开(公告)日：2020-10-06

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi Yamaha ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Kazuto Watanabe ,  Katsuya Kato ,  Hajime Yamamoto ,  Hiroshi Sasaki

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

公开(公告)号：US10790296B1

公开(公告)日：2020-09-29

申请号：US16417913

申请日：2019-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Yamaha ,  Katsuya Kato ,  Kazuto Watanabe ,  Hajime Yamamoto ,  Michiaki Sano ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Hiroshi Sasaki

IPC: H01L29/792 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11551

Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.