公开(公告)号：US10181442B1

公开(公告)日：2019-01-15

申请号：US15826796

申请日：2017-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11529 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L27/11514 ,  H01L27/06 ,  H01L27/11578

Abstract: A three-dimensional memory device includes an alternating stack of L-shaped insulating layers and L-shaped electrically conductive layers located over a top surface of a substrate, such that each of the L-shaped insulating layers and the L-shaped electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the alternating stack that includes the horizontally-extending portions of the L-shaped electrically conductive layers, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, dielectric spacers non-horizontally extending between neighboring pairs of a non-horizontally-extending portion of an L-shaped insulating layer and a non-horizontally-extending portion of an L-shaped electrically conductive layer, and contact via structures that contact a respective one of the non-horizontally-extending portions of the L-shaped electrically conductive layers.

公开(公告)号：US12256544B2

公开(公告)日：2025-03-18

申请号：US17682550

申请日：2022-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Watanabe ,  Youko Furihata

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.

公开(公告)号：US10211215B1

公开(公告)日：2019-02-19

申请号：US15895102

申请日：2018-02-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yashushi Ishii ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi ,  Tae-Kyung Kim

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11597 ,  H01L27/28 ,  H01L27/11529 ,  H01L27/105 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11514 ,  H01L45/00

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Each of the first insulating layers and the first sacrificial material layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion. Memory stack structures are formed through the horizontally-extending portions of the alternating stack. Regions of the non-horizontally-extending portions of the sacrificial material layers are masked with patterned etch mask portions. Unmasked first regions of the non-horizontally-extending portions of the first sacrificial material layers are selectively recessed, and the sacrificial material layers with electrically conductive layers. Each electrically conductive layer can include a vertical plate region and a protrusion region that protrudes above the vertical plate region and having a narrower lateral dimension that the vertical plate region. Metal contact structures can be formed on the protrusion regions without contacting the vertical plate regions.

公开(公告)号：US11812598B2

公开(公告)日：2023-11-07

申请号：US17355883

申请日：2021-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Watanabe

IPC: H10B43/27 ,  H10B43/35 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.

公开(公告)号：US10797035B1

公开(公告)日：2020-10-06

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi Yamaha ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Kazuto Watanabe ,  Katsuya Kato ,  Hajime Yamamoto ,  Hiroshi Sasaki

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

公开(公告)号：US10790296B1

公开(公告)日：2020-09-29

申请号：US16417913

申请日：2019-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Yamaha ,  Katsuya Kato ,  Kazuto Watanabe ,  Hajime Yamamoto ,  Michiaki Sano ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Hiroshi Sasaki

IPC: H01L29/792 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11551

Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

公开(公告)号：US10217746B1

公开(公告)日：2019-02-26

申请号：US15867881

申请日：2018-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tae-Kyung Kim ,  Raghuveer S. Makala ,  Yanli Zhang ,  Hiroyuki Kinoshita ,  Daxin Mao ,  Jixin Yu ,  Yiyang Gong ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi

IPC: H01L27/105 ,  H01L21/768 ,  H01L27/24 ,  H01L23/535 ,  H01L45/00

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers.