-
公开(公告)号：US11532570B2
公开(公告)日：2022-12-20
申请号：US17174064
申请日：2021-02-11
发明人： Genta Mizuno , Kenzo Iizuka , Satoshi Shimizu , Keisuke Izumi , Tatsuya Hinoue , Yujin Terasawa , Seiji Shimabukuro , Ryousuke Itou , Yanli Zhang , Johann Alsmeier , Yusuke Yoshida
IPC分类号： H01L27/11556 , H01L23/00 , H01L27/11582 , H01L23/522
摘要： A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.
-
公开(公告)号：US20180342531A1
公开(公告)日：2018-11-29
申请号：US15607583
申请日：2017-05-29
发明人： Hiromasa Susuki , Masanori Tsutsumi , Shigehisa Inoue , Junji Oh , Kensuke Yamaguchi , Seiji Shimabukuro , Yuji Fukano , Ryoichi Ehara , Youko Furihata
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.
-
公开(公告)号：US09608043B2
公开(公告)日：2017-03-28
申请号：US15161767
申请日：2016-05-23
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
-
4.发明申请THREE DIMENSIONAL MEMORY DEVICE HAVING WELL CONTACT PILLAR AND METHOD OF MAKING THEREOF 审中-公开具有良好接触柱的三维存储器件及其制造方法公开(公告)号：US20160329341A1
公开(公告)日：2016-11-10
申请号：US15216941
申请日：2016-07-22
IPC分类号： H01L27/115 , H01L23/522
CPC分类号： H01L27/11556 , G11C5/02 , G11C16/0408 , G11C16/0483 , G11C2213/71 , H01L23/5226 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.
摘要翻译： 单片三维存储器件包括具有基本上平行于半导体衬底的主表面延伸的第一导电类型的主表面和掺杂阱区的半导体衬底，多个NAND存储器串，基本上垂直于半导体衬底的主表面延伸 所述半导体衬底以及基本上垂直于所述半导体衬底的主表面延伸的多个基本上柱状的支撑构件，每个支撑构件包括围绕导电芯材的电绝缘外部材料，所述导电芯材基本上垂直于所述半导体衬底的主表面延伸 半导体衬底并与掺杂阱区电接触。
-
5.发明申请公开(公告)号：US20190312035A1
公开(公告)日：2019-10-10
申请号：US15947378
申请日：2018-04-06
IPC分类号： H01L27/105 , H01L21/30 , H01L23/528 , H01L21/822 , H01L25/065 , H01L27/11524 , H01L27/11529
摘要： A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers.
-
公开(公告)号：US10354859B1
公开(公告)日：2019-07-16
申请号：US15920793
申请日：2018-03-14
IPC分类号： H01L21/02 , H01L27/24 , H01L45/00 , G11C13/00 , H01L21/8229 , H01L21/8238 , H01L21/8234 , H01L21/822 , H01L21/8232
摘要： An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.
-
公开(公告)号：US10141331B1
公开(公告)日：2018-11-27
申请号：US15607583
申请日：2017-05-29
发明人： Hiromasa Susuki , Masanori Tsutsumi , Shigehisa Inoue , Junji Oh , Kensuke Yamaguchi , Seiji Shimabukuro , Yuji Fukano , Ryoichi Ehara , Youko Furihata
IPC分类号： H01L29/76 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.
-
8.发明申请METHOD OF OPERATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES 有权具有分开的APART位线和部分分开的位线选择开关的存储器阵列的操作方法公开(公告)号：US20160268340A1
公开(公告)日：2016-09-15
申请号：US15161767
申请日：2016-05-23
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
摘要翻译： 非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。 紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出 并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。 编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。
-
公开(公告)号：US11844222B2
公开(公告)日：2023-12-12
申请号：US17146866
申请日：2021-01-12
发明人： Shunsuke Takuma , Yuji Totoki , Seiji Shimabukuro , Tatsuya Hinoue , Kengo Kajiwara , Akihiro Tobioka
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.
-
10.发明申请公开(公告)号：US20200006131A1
公开(公告)日：2020-01-02
申请号：US16023174
申请日：2018-06-29
发明人： Seiji Shimabukuro , Makoto Kamijo , Tetsuya Kaneko
IPC分类号： H01L21/768 , H01L23/532 , H01L27/115
摘要： A first metal interconnect structure embedded in a first dielectric material layer includes a first metallic nitride liner containing a first conductive metal nitride and a first metallic fill material portion. A second metal interconnect structure embedded in a second dielectric material layer overlies the first dielectric material layer. The second metal interconnect structure includes a pillar portion having a straight sidewall and a foot portion adjoined to a bottom periphery of the pillar portion and laterally protruding from the bottom periphery of the pillar portion. The foot portion can be formed by oxidizing a top surface of the first metallic fill material portion, removing the oxidized portion after formation of a cavity through the second dielectric material layer, and depositing a second metallic nitride liner in a volume from which the oxidized portion is removed.
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.023 秒)
