公开(公告)号：US20200234743A1

公开(公告)日：2020-07-23

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US10734048B2

公开(公告)日：2020-08-04

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/08 ,  G11C7/12

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US20190371380A1

公开(公告)日：2019-12-05

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/12 ,  G11C7/08

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US10832770B2

公开(公告)日：2020-11-10

申请号：US16352749

申请日：2019-03-13

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma ,  Yadhu Vamshi Vancha ,  Jeffrey Lee

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.

公开(公告)号：US10803912B2

公开(公告)日：2020-10-13

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.