公开(公告)号：US3613017A

公开(公告)日：1971-10-12

申请号：US3613017D

申请日：1969-04-28

Applicant: SCIENCE ACCESSORIES CORP

Inventor： HOWELLS JOSEPH A

IPC: H01L21/00 ,  H03K3/284 ,  H03K5/04 ,  H03K19/003 ,  H03K3/10 ,  H03K3/12 ,  H03K17/30

CPC classification number: H03K19/00392 ,  H01L21/00 ,  H03K3/284 ,  H03K5/04

Abstract: A monostable multivibrator circuit for producing a pulse of a fixed duration including a first D-type flip-flop having set, reset, clock and delay inputs, and a second D-type flip-flop having set, reset, clock and delay inputs. A trigger pulse triggers a change in state of the first D-type flip-flop, in turn causing a change in state in the second D-type flip-flop. The output of the second D-type flip-flop contains a capacitor storage circuit which serves to bypass the change in state of the second D-type flip-flop for a predetermined delay time, and feedback an exponentially increasing level to the first D-type flip-flop. When the charge across the capacitor reaches the threshold level of the first D-type flip-flop, the first flipflop output again changes condition, causing the second output to change correspondingly.

公开(公告)号：US3568060A

公开(公告)日：1971-03-02

申请号：US3568060D

申请日：1967-10-18

Applicant: SCIENCE ACCESSORIES CORP

Inventor： HOWELLS JOSEPH A

IPC: H01J47/10 ,  H03K5/1532 ,  G04F9/00

CPC classification number: H03K5/1532 ,  H01J47/10

Abstract: A device for digitally indicating the center of a pulse employing a pulse counter and a pulse generator having a fixed generating rate. Upon receipt of an initial pulse a first flipflop opens a first gating circuit and passes pulses to the counter. A second flip-flop receives the leading edge of a subsequent pulse to turn off the first gate and opens a second gate. The second gate in turn allows pulses at one-half the fixed generating rate to accumulate in the counter. The trailing edge of the second pulse changes the state of the second flip-flop and turns off the second gate. The accumulated count is now representative of the measure from the initial timing pulse to the center of the second pulse. A further flip-flop, upon receipt of a further pulse, changes state and insures that the gating circuits do not open to permit further counting. The two level counting is accomplished by a pulse frequency dividing stage connected to the pulse source, or, alternatively, by using the output of the first counter stage.