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公开(公告)号：US5539347A
公开(公告)日：1996-07-23
申请号：US393580
申请日：1995-02-23
申请人： Kevin G. Duesman
发明人： Kevin G. Duesman
CPC分类号： H03K17/22
摘要： A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.
摘要翻译： 响应于主电源的应用的电路产生信号以建立逻辑电路的初始状态。 生成的信号插入到逻辑电路的输入信号线上，直到初始化完成。 在初始化之后，逻辑电路的输入信号线被重新连接以进行正常操作。
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公开(公告)号：US5306959A
公开(公告)日：1994-04-26
申请号：US858252
申请日：1992-03-26
申请人： Guenter Knauft , Bernd Leppla , Dietmar Schmunkamp , Ulrich Weiss
发明人： Guenter Knauft , Bernd Leppla , Dietmar Schmunkamp , Ulrich Weiss
CPC分类号： H03K5/15
摘要： An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.
摘要翻译： 一种用于为包含时钟生成芯片和各种逻辑电路芯片的多芯片计算机系统产生时钟脉冲的电路。 逻辑电路芯片上使用的时钟脉冲在时钟产生芯片上产生并被传送到逻辑电路芯片。 为了产生时钟脉冲，在时钟产生电路上提供所谓的时钟分配器电路。 该时钟分配器产生从振荡器导出的第三脉冲串中的两个脉冲串。 时钟分配器包含多个门和锁存器，这些门和锁存器对脉冲通过时钟分配器的吞吐量时间以及两个产生的脉冲串的偏斜有影响。 本发明提供了一种电路，其具有改善的生成时间和产生的脉冲串的偏斜。
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公开(公告)号：US5298799A
公开(公告)日：1994-03-29
申请号：US999050
申请日：1992-12-31
CPC分类号： H03K3/033
摘要： The provision of a clock chopper, pulse shaper, single-shot circuit with NOR gates a delay path and a set-reset latch. In response to a high input (for example) to a first NOR gate, the circuit output goes high and remains high until the output of the one NOR gate propagates through the delay one input of a second NOR gate whose other input is coupled to a set-reset latch. When the delayed output of the first NOR gate reaches the input of the second NOR gate, the circuit output falls, and the change in circuit output is fed back to reset the latch. The change in latch state changes the output state of the second NOR gate and resets the circuit for next input.
摘要翻译： 提供时钟斩波器，脉冲整形器，NOR门的单路电路延迟路径和设置复位锁存器。 响应于第一或非门的高输入（例如），电路输出变高并保持高电平，直到一个或非门的输出传播通过第二或非门的延迟一个输入，其另一个输入耦合到 设置复位锁存器。 当第一或非门的延迟输出到达第二或非门的输入时，电路输出下降，电路输出的变化被反馈以复位锁存器。 锁存状态的改变会改变第二个或非门的输出状态，并复位下一个输入的电路。
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公开(公告)号：US4812752A
公开(公告)日：1989-03-14
申请号：US110170
申请日：1987-10-19
申请人： Ernest A. Preuss
发明人： Ernest A. Preuss
CPC分类号： G01R31/045 , G01R27/2605 , G01R31/026
摘要： A circuit tester provides an indication of open circuit faults of individual conductors in cables. An oscillator circuit in the tesster includes a capacitance as an internal part of the circuit. Test probes connect conductor pairs to the oscillator circuit, thus changing the effective capacitance of the circuit. This changes the frequency output of the oscillator in accordance with the length of the conductors. Test indications may include a low pass filter and an audio circuit, or a circuit to convert frequency to a voltage or digitalized output. The tester may be used with automated test equipment.
摘要翻译： 电路测试仪提供电缆中各个导线的开路故障指示。 特斯特斯中的振荡器电路包括作为电路的内部部分的电容。 测试探针将导体对连接到振荡器电路，从而改变电路的有效电容。 这会根据导体的长度改变振荡器的频率输出。 测试指示可以包括低通滤波器和音频电路，或者将频率转换成电压或数字化输出的电路。 测试仪可与自动测试设备一起使用。
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公开(公告)号：US4806786A
公开(公告)日：1989-02-21
申请号：US115953
申请日：1987-11-02
申请人： William R. Valentine
发明人： William R. Valentine
IPC分类号： H03K3/3562 , H03K3/26 , H03K3/284 , H03K17/16
CPC分类号： H03K3/35625
摘要： A latch circuit is provided which may be set to a predetermined logic state in response to a positive transitioning edge of a set signal and reset to an opposite logic state in response to a negative transitioning edge of a rest signal. A master circuit portion receives the set and reset signals and provides a control signal in response to the set and reset signals and the output signal. A slave circuit portion receives the control signal and provides the output signal in response to the control signal and the set and reset signals. By multiplexing set and reset enabling functions with common circuitry, a reduced amount of circuitry is required.
摘要翻译： 提供了一个锁存电路，其可以响应于设定信号的正转换边缘而被设置为预定的逻辑状态，并且响应于静止信号的负转变边缘而复位到相反的逻辑状态。 主电路部分接收设置和复位信号，并响应于设置和复位信号和输出信号提供控制信号。 从电路部分接收控制信号并响应于控制信号和设置和复位信号提供输出信号。 通过使用公共电路复用设置和复位使能功能，需要减少量的电路。
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公开(公告)号：US4797576A
公开(公告)日：1989-01-10
申请号：US81877
申请日：1987-08-05
申请人： Hiroshi Asazawa
发明人： Hiroshi Asazawa
IPC分类号： H03K3/012 , H03K3/037 , H03K19/173 , H03K3/284 , H03K3/29
摘要： In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected. Latch switches are inserted between the inverters and the corresponding data input terminals. Hold switches are inserted in the cross-connected portion of the two inverters. The latch switches are turned on/off in synchronism with a latch input while the hold switches are turned on/off in synchronism with a hold input.
摘要翻译： 在触发电路中，连接在相应的数据输入端子和对应的数据输出端子之间的两个逆变器的输入和输出端子是交叉连接的。 变频器和相应的数据输入端子之间插入有锁存开关。 保持开关插入两个逆变器的交叉连接部分。 锁定开关与锁存器输入同步打开/关闭，同时保持开关与保持输入同步打开/关闭。
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公开(公告)号：US4779009A
公开(公告)日：1988-10-18
申请号：US886828
申请日：1986-07-18
申请人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
发明人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
CPC分类号： H03K3/289
摘要： In a master-slave type flip-flop circuit including a normal function in a normal mode for flip/flop operation and a scanning function in a scanning mode for testing an integrated circuit, the master-slave type flip-flop circuit comprises: a master stage having a first pair of differential transistors for taking in data, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for taking in scanning data, and a fourth pair of differential transistors for activating the second and third pair of differential transistors in the scanning mode; and a slave stage having a first pair of differential transistors for taking in data from the master stage, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for latching scanning data, and a fourth pair of differential transistors for activating the first and third pair of differential transistors in the scanning mode.
摘要翻译： 主从型触发电路包括：主从触发器电路，包括用于触发/翻转操作的正常模式的正常功能和用于测试集成电路的扫描模式的扫描功能，主从触发器电路包括：主器件 阶段具有用于接收数据的第一对差分晶体管，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于接收扫描数据的第三对差分晶体管和第四对差分 用于在扫描模式下激活第二和第三对差分晶体管的晶体管; 以及具有用于从主级接收数据的第一对差分晶体管的子级，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于锁存扫描数据的第三对差分晶体管， 以及第四对差分晶体管，用于在扫描模式下激活第一和第三对差分晶体管。
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公开(公告)号：US4691122A
公开(公告)日：1987-09-01
申请号：US717350
申请日：1985-03-29
IPC分类号： H01L27/11 , G11C11/41 , G11C19/28 , H01L21/8244 , H01L27/10 , H03K3/037 , H03K3/356 , H03K3/3562 , H03K3/26 , H03K3/284 , H03K17/16 , H03K19/096
CPC分类号： H03K3/356104 , G11C19/28 , H03K3/3562
摘要： A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.
摘要翻译： 用于避免馈通的可能性的CMOS D型触发器电路级包括具有真实时钟输出和补码时钟输出的非重叠时钟发生器部分。 触发器电路包括由第一传输栅极，第一再生晶体管和第一反相器栅极形成的主部分。 触发器电路还包括由第二传输栅极，第二再生晶体管和第二反相器栅极形成的从部分。 时钟发生器提供两相不重叠的时钟，用于对主部分和从部分进行计时，以防止数据输入到连续阶段的无意中的穿通。
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公开(公告)号：US4689497A
公开(公告)日：1987-08-25
申请号：US740766
申请日：1985-06-03
申请人： Yoshitaka Umeki , Kazuyoshi Yamada
发明人： Yoshitaka Umeki , Kazuyoshi Yamada
IPC分类号： H03K3/289 , H03K3/037 , H03K3/2885 , H03K3/3562 , H03K3/284
CPC分类号： H03K3/2885 , H03K3/0372
摘要： In a master-slave type flip-flop circuit, a plurality of bipolar type transistors are used for master and slave flip-flop circuits, and transistors are connected such that glitch noise can be prevented under all input conditions.
摘要翻译： 在主从型触发器电路中，多个双极型晶体管用于主从触发电路，并且连接晶体管，使得可以在所有输入条件下防止毛刺噪声。
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公开(公告)号：US4667118A
公开(公告)日：1987-05-19
申请号：US701353
申请日：1985-02-13
申请人： Shuichiro Maruta
发明人： Shuichiro Maruta
摘要： There is disclosed a monostable multivibrator in which a latch circuit or flip-flop circuit and a comparator circuit are separated. The comparator circuit compares a reference potential and an output potential of a time constant circuit and produces an output signal. The flip-flop circuit is controlled in accordance with an output signal of the comparator circuit.
摘要翻译： 公开了一种单稳态多谐振荡器，其中分离了锁存电路或触发器电路和比较器电路。 比较器电路比较时间常数电路的参考电位和输出电位，并产生输出信号。 触发器电路根据比较器电路的输出信号进行控制。
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